JAJSEE3D January   2018  – January 2021 MSP430FR2422

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 機能ブロック図
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Types
    6. 7.6 Connection of Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode (LPM0) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics - Low-Power Mode Supply Currents
    10. 8.10 Typical Characteristics – Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Typical Characteristics – Outputs at 3 V and 2 V
      5. 8.12.5  VREF+ Built-in Reference
        1. 8.12.5.1 VREF+
      6. 8.12.6  Timer_A
        1. 8.12.6.1 Timer_A
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode)
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode)
        5. 8.12.7.5 eUSCI (SPI Slave Mode)
        6. 8.12.7.6 eUSCI (I2C Mode)
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, 10-Bit Timing Parameters
        3. 8.12.8.3 ADC, 10-Bit Linearity Parameters
      9. 8.12.9  FRAM
        1. 8.12.9.1 FRAM
      10. 8.12.10 Debug and Emulation
        1. 8.12.10.1 JTAG, Spy-Bi-Wire Interface
        2. 8.12.10.2 JTAG, 4-Wire Interface
  9. Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Standard Interface
    7. 9.7  Spy-Bi-Wire Interface (SBW)
    8. 9.8  FRAM
    9. 9.9  Memory Protection
    10. 9.10 Peripherals
      1. 9.10.1  Power-Management Module (PMM)
      2. 9.10.2  Clock System (CS) and Clock Distribution
      3. 9.10.3  General-Purpose Input/Output Port (I/O)
      4. 9.10.4  Watchdog Timer (WDT)
      5. 9.10.5  System (SYS) Module
      6. 9.10.6  Cyclic Redundancy Check (CRC)
      7. 9.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.10.8  Timers (Timer0_A3, Timer1_A3)
      9. 9.10.9  Hardware Multiplier (MPY)
      10. 9.10.10 Backup Memory (BAKMEM)
      11. 9.10.11 Real-Time Clock (RTC)
      12. 9.10.12 10-Bit Analog-to-Digital Converter (ADC)
      13. 9.10.13 Embedded Emulation Module (EEM)
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.11.2 Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors
    13. 9.13 Memory
      1. 9.13.1 Memory Organization
      2. 9.13.2 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Revision Identification
      2. 9.14.2 Device Identification
      3. 9.14.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Export Control Notice
    9. 11.9 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • PW|16
  • RHL|20
サーマルパッド・メカニカル・データ
発注情報

eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSVCCMINMAXUNIT
tSTE,LEADSTE lead time, STE active to clock2 V55ns
3 V45
tSTE,LAGSTE lag time, Last clock to STE inactive2 V20ns
3 V20
tSTE,ACCSTE access time, STE active to SOMI data out2 V65ns
3 V40
tSTE,DISSTE disable time, STE inactive to SOMI high impedance2 V40ns
3 V35
tSU,SISIMO input data setup time2 V8ns
3 V6
tHD,SISIMO input data hold time2 V12ns
3 V12
tVALID,SOSOMI output data valid time(2)UCLK edge to SOMI valid,
CL = 20 pF
2 V68ns
3 V42
tHD,SOSOMI output data hold time (3)CL = 20 pF2 V5ns
3 V5
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 8-15 and Figure 8-16.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 8-15 and Figure 8-16.
GUID-AAF68A02-C2C0-4E02-BBFB-0CD3F51BA254-low.gifFigure 8-15 SPI Slave Mode, CKPH = 0
GUID-545434B5-9B17-4CB9-9BDE-62564E69E5FF-low.gifFigure 8-16 SPI Slave Mode, CKPH = 1

Section 8.12.7.6 lists the characteristics of the eUSCI in I2C mode.