JAJSG08E November 2015 – December 2019 MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK or MODCLK,
External: UCLK Duty cycle = 50% ±10% |
16 | MHz | |||
fSCL | SCL clock frequency | 2 V, 3 V | 0 | 400 | kHz | ||
tHD,STA | Hold time (repeated) START | fSCL = 100 kHz | 2 V, 3 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSU,STA | Setup time for a repeated START | fSCL = 100 kHz | 2 V, 3 V | 4.7 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tHD,DAT | Data hold time | 2 V, 3 V | 0 | ns | |||
tSU,DAT | Data setup time | 2 V, 3 V | 250 | ns | |||
tSU,STO | Setup time for STOP | fSCL = 100 kHz | 2 V, 3 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSP | Pulse duration of spikes suppressed by input filter | UCGLITx = 0 | 2 V, 3 V | 50 | 600 | ns | |
UCGLITx = 1 | 25 | 300 | |||||
UCGLITx = 2 | 12.5 | 150 | |||||
UCGLITx = 3 | 6.3 | 75 | |||||
tTIMEOUT | Clock low time-out | UCCLTOx = 1 | 2 V, 3 V | 27 | ms | ||
UCCLTOx = 2 | 30 | ||||||
UCCLTOx = 3 | 33 |