JAJSH23D March   2019  – September 2021 MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Types
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Typical Characteristics – Outputs at 3 V and 2 V
      5. 8.12.5  Internal Shared Reference
        1. 8.12.5.1 Internal Reference Characteristics
      6. 8.12.6  Timer_A and Timer_B
        1. 8.12.6.1 Timer_A
        2. 8.12.6.2 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Timing Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode)
        5. 8.12.7.5 eUSCI (SPI Slave Mode)
        6. 8.12.7.6 eUSCI (I2C Mode)
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, Timing Parameters
        3. 8.12.8.3 ADC, Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP0 Characteristics
      10. 8.12.10 CapTIvate
        1. 8.12.10.1 CapTIvate Electrical Characteristics
        2. 8.12.10.2 CapTIvate Signal-to-Noise Ratio Characteristics
      11. 8.12.11 FRAM
        1. 8.12.11.1 FRAM Characteristics
      12. 8.12.12 Debug and Emulation
        1. 8.12.12.1 JTAG, 4-Wire and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Standard Interface
    7. 9.7  Spy-Bi-Wire Interface (SBW)
    8. 9.8  FRAM
    9. 9.9  Memory Protection
    10. 9.10 Peripherals
      1. 9.10.1  Power-Management Module (PMM)
      2. 9.10.2  Clock System (CS) and Clock Distribution
      3. 9.10.3  General-Purpose Input/Output Port (I/O)
      4. 9.10.4  Watchdog Timer (WDT)
      5. 9.10.5  System (SYS) Module
      6. 9.10.6  Cyclic Redundancy Check (CRC)
      7. 9.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.10.8  Timers (TA0, TA1, TA2, TA3 and TB0)
      9. 9.10.9  Hardware Multiplier (MPY)
      10. 9.10.10 Backup Memory (BAKMEM)
      11. 9.10.11 Real-Time Clock (RTC)
      12. 9.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 9.10.13 eCOMP0
      14. 9.10.14 CapTIvate Technology
      15. 9.10.15 Embedded Emulation Module (EEM)
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.11.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.11.5 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      6. 9.11.6 Port P6 (P6.0 to P6.2) Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors
    13. 9.13 Memory
      1. 9.13.1 Memory Organization
      2. 9.13.2 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Revision Identification
      2. 9.14.2 Device Identification
      3. 9.14.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
      2. 10.2.2 CapTIvate Peripheral
        1. 10.2.2.1 Device Connection and Layout Fundamentals
        2. 10.2.2.2 125
        3. 10.2.2.3 Measurements
          1. 10.2.2.3.1 SNR
          2. 10.2.2.3.2 Sensitivity
          3. 10.2.2.3.3 Power
    3. 10.3 CapTIvate Technology Evaluation
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3 Signal Descriptions

Table 7-2 describes the signals for all device variants and package options.

Table 7-2 Signal Descriptions
FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE(1) DESCRIPTION
PT RHA RHB
ADC A0 12 10 7 I Analog input A0
A1 13 11 8 I Analog input A1
A2 14 12 9 I Analog input A2
A3 15 13 10 I Analog input A3
A4 4 4 3 I Analog input A4
A5 5 5 4 I Analog input A5
A6 6 6 5 I Analog input A6
A7 7 7 6 I Analog input A7
A8 8 8 – I Analog input A8
A9 9 9 – I Analog input A9
A10 10 – – I Analog input A10
A11 11 – – I Analog input A11
Veref+ 12 10 7 I ADC positive reference
Veref- 14 12 9 I ADC negative reference
eCOMP0 COMP0.0 13 11 8 I Enhanced comparator input channel C0
COMP0.1 16 14 11 I Enhanced comparator input channel C1
COMP0.2 21 – – I Enhanced comparator input channel C2
COMP0.3 22 – – I Enhanced comparator input channel C3
COMP0OUT 26 20 15 O Enhanced comparator output channel COUT
CapTIvate CAP0.0 23 17 12 I/O CapTIvate channel
CAP0.1 24 18 13 I/O CapTIvate channel
CAP0.2 25 19 14 I/O CapTIvate channel
CAP0.3 26 20 15 I/O CapTIvate channel
CAP1.0 27 21 16 I/O CapTIvate channel
CAP1.1 28 22 17 I/O CapTIvate channel
CAP1.2 29 23 18 I/O CapTIvate channel
CAP1.3 30 24 19 I/O CapTIvate channel
CAP2.0 32 26 21 I/O CapTIvate channel
CAP2.1 33 27 22 I/O CapTIvate channel
CAP2.2 34 28 23 I/O CapTIvate channel
CAP2.3 35 29 24 I/O CapTIvate channel
CAP3.0 36 30 25 I/O CapTIvate channel
CAP3.1 37 31 26 I/O CapTIvate channel
CAP3.2 38 32 27 I/O CapTIvate channel
CAP3.3 39 33 28 I/O CapTIvate channel
SYNC 16 14 11 I CapTIvate synchronous trigger input for processing and conversion
Clock ACLK 16 14 11 I/O ACLK output
MCLK 15 13 10 O MCLK output
SMCLK 7 7 6 O SMCLK output
XIN 47 39 30 I Input terminal for crystal oscillator
XOUT 46 38 29 O Output terminal for crystal oscillator
Debug SBWTCK 3 3 2 I Spy-Bi-Wire input clock
SBWTDIO 2 2 1 I/O Spy-Bi-Wire data input/output
TCK 4 4 3 I Test clock
TCLK 6 6 5 I Test clock input
TDI 6 6 5 I Test data input
TDO 7 7 6 O Test data output
TEST 3 3 2 I Test Mode pin – selected digital I/O on JTAG pins
TMS 5 5 4 I Test mode select
GPIO, Port 1 P1.0 12 10 7 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P1.1 13 11 8 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P1.2 14 12 9 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P1.3 15 13 10 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P1.4 4 4 3 I/O General-purpose I/O with port interrupt and wake from LPMx.5 (2)
P1.5 5 5 4 I/O General-purpose I/O with port interrupt and wake from LPMx.5(2)
P1.6 6 6 5 I/O General-purpose I/O with port interrupt and wake from LPMx.5(2)
P1.7 7 7 6 I/O General-purpose I/O with port interrupt and wake from LPMx.5(2)
GPIO, Port 2 P2.0 46 38 29 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.1 47 39 30 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.2 16 14 11 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.3 25 19 14 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.4 28 22 17 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.5 29 23 18 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.6 30 24 19 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.7 36 30 25 I/O General-purpose I/O with port interrupt and wake from LPMx.5
GPIO, Port 3 P3.0 23 17 12 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.1 27 21 16 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.2 38 32 27 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.3 24 18 13 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.4 26 20 15 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.5 37 31 26 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.6 39 33 28 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.7 32 26 21 I/O General-purpose I/O with port interrupt and wake from LPMx.5
GPIO, Port 4 P4.0 33 27 22 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.1 34 28 23 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.2 35 29 24 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.3 8 8 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.4 9 9 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.5 17 15 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.6 18 16 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.7 42 34 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
GPIO, Port 5 P5.0 43 35 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.1 44 36 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.2 45 37 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.3 10 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.4 11 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.5 19 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.6 20 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.7 21 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
GPIO, Port 6 P6.0 22 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P6.1 40 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P6.2 41 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
I2C UCB0SCL(3) 15 13 10 I/O eUSCI_B0 I2C clock
UCB0SDA(3) 14 12 9 I/O eUSCI_B0 I2C data
UCB0SCL(4) 17 15 – I/O eUSCI_B0 I2C clock
UCB0SDA(4) 18 16 – I/O eUSCI_B0 I2C data
UCB1SCL(3) 39 33 28 I/O eUSCI_B1 I2C clock
UCB1SDA(3) 38 32 27 I/O eUSCI_B1 I2C data
UCB1SCL(4) 8 8 – I/O eUSCI_B1 I2C clock
UCB1SDA(4) 9 9 – I/O eUSCI_B1 I2C data
Power DVCC 1 1 32 P Power supply
DVSS 48 40 31 P Power ground
VREF+ 4 4 3 P Output of positive reference voltage with ground as reference
VREG 31 25 20 O CapTIvate regulator external decoupling capacitor
SPI UCA0STE(3) 7 7 6 I/O eUSCI_A0 SPI slave transmit enable
UCA0CLK(3) 6 6 5 I/O eUSCI_A0 SPI clock input/output
UCA0SOMI(3) 5 5 4 I/O eUSCI_A0 SPI slave out/master in
UCA0SIMO(3) 4 4 3 I/O eUSCI_A0 SPI slave in/master out
UCA0STE(4) 42 34 – I/O eUSCI_A0 SPI slave transmit enable
UCA0CLK(4) 43 35 – I/O eUSCI_A0 SPI clock input/output
UCA0SOMI(4) 44 36 – I/O eUSCI_A0 SPI slave out/master in
UCA0SIMO(4) 45 37 – I/O eUSCI_A0 SPI slave in/master out
UCA1STE 27 21 16 I/O eUSCI_A1 SPI slave transmit enable
UCA1CLK 28 22 17 I/O eUSCI_A1 SPI clock input/output
UCA1SOMI 29 23 18 I/O eUSCI_A1 SPI slave out/master in
UCA1SIMO 30 24 19 I/O eUSCI_A1 SPI slave in/master out
UCB0STE(3) 12 10 7 I/O eUSCI_B0 slave transmit enable
UCB0CLK(3) 13 11 8 I/O eUSCI_B0 clock input/output
UCB0SOMI(3) 15 13 10 I/O eUSCI_B0 SPI slave out/master in
UCB0SIMO(3) 14 12 9 I/O eUSCI_B0 SPI slave in/master out
UCB0STE(4) 20 – – I/O eUSCI_B0 slave transmit enable
UCB0CLK(4) 19 – – I/O eUSCI_B0 clock input/output
UCB0SOMI(4) 17 – – I/O eUSCI_B0 SPI slave out/master in
UCB0SIMO(4) 18 – – I/O eUSCI_B0 SPI slave in/master out
UCB1STE(3) 36 30 25 I/O eUSCI_B1 slave transmit enable
UCB1CLK(3) 37 31 26 I/O eUSCI_B1 clock input/output
UCB1SOMI(3) 39 33 28 I/O eUSCI_B1 SPI slave out/master in
UCB1SIMO(3) 38 32 27 I/O eUSCI_B1 SPI slave in/master out
UCB1STE(4) 11 – – I/O eUSCI_B1 slave transmit enable
UCB1CLK(4) 10 – – I/O eUSCI_B1 clock input/output
UCB1SOMI(4) 8 – – I/O eUSCI_B1 SPI slave out/master in
UCB1SIMO(4) 9 – – I/O eUSCI_B1 SPI slave in/master out
System NMI 2 2 1 I Nonmaskable interrupt input
RST 2 2 1 I Active-low reset input
Timer_A TA0.1 13 11 8 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
TA0.2 14 12 9 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
TA0CLK 12 10 7 I Timer clock input TACLK for TA0
TA1.1 5 5 4 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
TA1.2 4 4 3 I/O Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
TA1CLK 6 6 5 I Timer clock input TACLK for TA1
TA2.0(5) 25 19 14 I/O Timer TA2 CCR0 capture: CCI0A input, compare: Out0 outputs
TA2.1(5) 24 18 13 I/O Timer TA2 CCR1 capture: CCI1A input, compare: Out1 outputs
TA2.2(5) 23 17 12 I/O Timer TA2 CCR2 capture: CCI2A input, compare: Out2 outputs
TA2CLK(5) 26 20 15 I Timer clock input TACLK for TA2
TA2.0(6) 20 – – I/O Timer TA2 CCR0 capture: CCI0A input, compare: Out0 outputs
TA2.1(6) 21 – – I/O Timer TA2 CCR1 capture: CCI1A input, compare: Out1 outputs
TA2.2(6) 22 – – I/O Timer TA2 CCR2 capture: CCI2A input, compare: Out2 outputs
TA2CLK(6) 19 – – I Timer clock input TACLK for TA2
TA3.0(5) 34 28 23 I/O Timer TA3 CCR0 capture: CCI0A input, compare: Out0 outputs
TA3.1(5) 33 27 22 I/O Timer TA3 CCR1 capture: CCI1A input, compare: Out1 outputs
TA3.2(5) 32 26 21 I/O Timer TA3 CCR2 capture: CCI2A input, compare: Out2 outputs
TA3CLK(5) 35 29 24 I Timer clock input TACLK for TA3
TA3.0(6) 10 – – I/O Timer TA3 CCR0 capture: CCI0A input, compare: Out0 outputs
TA3.1(6) 18 16 – I/O Timer TA3 CCR1 capture: CCI1A input, compare: Out1 outputs
TA3.2(6) 17 15 – I/O Timer TA3 CCR2 capture: CCI2A input, compare: Out2 outputs
TA3CLK(6) 11 – – I Timer clock input TACLK for TA3
Timer_B TB0.0 41 – – I/O Timer TB0 CCR0 capture: CCI0A input, compare: Out0 outputs
TB0.1 42 34 – I/O Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.2 43 35 – I/O Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
TB0.3 44 36 – I/O Timer TB0 CCR3 capture: CCI3A input, compare: Out3 outputs
TB0.4 45 37 – I/O Timer TB0 CCR4 capture: CCI4A input, compare: Out4 outputs
TB0.5 8 8 – I/O Timer TB0 CCR5 capture: CCI5A input, compare: Out5 outputs
TB0.6 9 9 – I/O Timer TB0 CCR6 capture: CCI6A input, compare: Out6 outputs
TB0CLK 40 – – I Timer clock input TBCLK for TB0
TB0TRG 37 31 26 Timer TB0 external trigger input for TB0OUTH
UART UCA0RXD 5 5 4 I eUSCI_A0 UART receive data
UCA0TXD 4 4 3 O eUSCI_A0 UART transmit data
UCA0RXD(3) 44 36 – I eUSCI_A0 UART receive data
UCA0TXD(3) 45 37 – O eUSCI_A0 UART transmit data
UCA1RXD(4) 29 23 18 I eUSCI_A1 UART receive data
UCA1TXD(4) 30 24 19 O eUSCI_A1 UART transmit data
VQFN pad VQFN thermal pad – PAD PAD – VQFN package exposed thermal pad. TI recommends connecting to VSS
(1) Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.
(3) This is the default functionality that can be remapped by the USCIBxRMP or USCIA0RMP bit of the SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.
(4) This is the remapped functionality controlled by the USCIBxRMP or USCIA0RMP bit of the SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.
(5) This is the default functionality that can be remapped by the TAxRMP bit of the SYSCFG3 register. Only one selected port is valid at any time.
(6) This is the remapped functionality controlled by the TAxRMP bit of the SYSCFG3 register. Only one selected port is valid at any time.