JAJSH23 データシート

JAJSH23D March 2019 – September 2021 MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PT|48
- MTQF003C
RHB|32
- MPQF130D
RHA|40
- MPQF135D

サーマルパッド・メカニカル・データ

RHB|32
- QFND029X
RHA|40
- QFND027R

発注情報

9.10.2 Clock System (CS) and Clock Distribution

The clock system includes a 32-kHz crystal oscillator (XT1), an internal very-low-power low-frequency oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock, and an on-chip asynchronous high-speed clock (MODOSC). The clock system is designed for cost-effective designs with minimal external components. A fail-safe mechanism is included for XT1. The clock system module offers the following clock signals.

Main Clock (MCLK): The system clock used by the CPU and all relevant peripherals accessed by the bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8, 16, 32, 64, or 128.
Sub-Main Clock (SMCLK): The subsystem clock used by the peripheral modules. SMCLK derives from the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
Auxiliary Clock (ACLK): This clock is derived from the external XT1 clock, internal VLO or internal REFO clock up to 40 kHz.

All peripherals may have one or several clock sources depending on specific functionality. Table 9-8 lists the clock distribution used in this device.

Table 9-8 Clock Distribution

	CLOCK SOURCE SELECT BITS	MCLK	SMCLK	ACLK	MODCLK	XT1CLK	VLOCLK	EXTERNAL PIN
Frequency range		DC to 16 MHz	DC to 16 MHz	DC to 40 kHz	5 MHz ±10%	DC to 40 kHz	10 kHz ±50%	–
CPU	N/A	Default	–	–	–	–	–	–
FRAM	N/A	Default	–	–	–	–	–	–
RAM	N/A	Default	–	–	–	–	–	–
CRC	N/A	Default	–	–	–	–	–	–
MPY32	N/A	Default	–	–	–	–	–	–
I/O	N/A	Default	–	–	–	–	–	–
TA0	TASSEL	–	10b	01b	–	–	11b	00b (TA0CLK pin)
TA1	TASSEL	–	10b	01b	–	–	–	00b (TA1CLK pin)
TA2	TASSEL	–	10b	01b	–	–	11b	00b (TA2CLK pin)
TA3	TASSEL	–	10b	01b	–	–	–	00b (TA3CLK pin)
TB0	TBSSEL	–	10b	01b	–	–	–	00b (TB0CLK pin)
eUSCI_A0	UCSSEL	–	10b or 11b	01b	–	–	–	00b (UCA0CLK pin)
eUSCI_A1	UCSSEL	–	10b or 11b	01b	–	–	–	00b (UCA1CLK pin)
eUSCI_B0	UCSSEL	–	10b or 11b	01b	–	–	–	00b (UCB0CLK pin)
eUSCI_B1	UCSSEL	–	10b or 11b	01b	–	–	–	00b (UCB1CLK pin)
WDT	WDTSSEL	–	00b	01b	–	–	10b	–
ADC	ADCSSEL	–	10b or 11b	01b	00b	–	–	–
CapTIvate	CAPTSSEL	–	–	00b	–	–	01b	–
RTC	RTCSS	–	01b⁽¹⁾	01b⁽¹⁾	–	10b	11b	–

(1) Controlled by the RTCCKSEL bit in the SYSCFG2 register.

Figure 9-1 Clock Distribution Block Diagram