JAJSH23D March   2019  – September 2021 MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Types
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Typical Characteristics – Outputs at 3 V and 2 V
      5. 8.12.5  Internal Shared Reference
        1. 8.12.5.1 Internal Reference Characteristics
      6. 8.12.6  Timer_A and Timer_B
        1. 8.12.6.1 Timer_A
        2. 8.12.6.2 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Timing Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode)
        5. 8.12.7.5 eUSCI (SPI Slave Mode)
        6. 8.12.7.6 eUSCI (I2C Mode)
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, Timing Parameters
        3. 8.12.8.3 ADC, Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP0 Characteristics
      10. 8.12.10 CapTIvate
        1. 8.12.10.1 CapTIvate Electrical Characteristics
        2. 8.12.10.2 CapTIvate Signal-to-Noise Ratio Characteristics
      11. 8.12.11 FRAM
        1. 8.12.11.1 FRAM Characteristics
      12. 8.12.12 Debug and Emulation
        1. 8.12.12.1 JTAG, 4-Wire and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Standard Interface
    7. 9.7  Spy-Bi-Wire Interface (SBW)
    8. 9.8  FRAM
    9. 9.9  Memory Protection
    10. 9.10 Peripherals
      1. 9.10.1  Power-Management Module (PMM)
      2. 9.10.2  Clock System (CS) and Clock Distribution
      3. 9.10.3  General-Purpose Input/Output Port (I/O)
      4. 9.10.4  Watchdog Timer (WDT)
      5. 9.10.5  System (SYS) Module
      6. 9.10.6  Cyclic Redundancy Check (CRC)
      7. 9.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.10.8  Timers (TA0, TA1, TA2, TA3 and TB0)
      9. 9.10.9  Hardware Multiplier (MPY)
      10. 9.10.10 Backup Memory (BAKMEM)
      11. 9.10.11 Real-Time Clock (RTC)
      12. 9.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 9.10.13 eCOMP0
      14. 9.10.14 CapTIvate Technology
      15. 9.10.15 Embedded Emulation Module (EEM)
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.11.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.11.5 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      6. 9.11.6 Port P6 (P6.0 to P6.2) Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors
    13. 9.13 Memory
      1. 9.13.1 Memory Organization
      2. 9.13.2 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Revision Identification
      2. 9.14.2 Device Identification
      3. 9.14.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
      2. 10.2.2 CapTIvate Peripheral
        1. 10.2.2.1 Device Connection and Layout Fundamentals
        2. 10.2.2.2 125
        3. 10.2.2.3 Measurements
          1. 10.2.2.3.1 SNR
          2. 10.2.2.3.2 Sensitivity
          3. 10.2.2.3.3 Power
    3. 10.3 CapTIvate Technology Evaluation
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.10.8 Timers (TA0, TA1, TA2, TA3 and TB0)

The TA0, TA1, TA2 and TA3 modules are 16-bit timers and counters with three capture/compare registers each. Each timer supports multiple captures or compares, PWM outputs, and interval timing (see Table 9-12 and Table 9-13). Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. The CCR0 registers on both TA0 and TA2 are not externally connected and can only be used for hardware period timing and interrupt generation. In Up mode, they can be used to set the overflow value of the counter.

Table 9-12 Timer0_A0 Signal Connections
PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P1.0 TA0CLK TACLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
VLO (internal) INCLK
ACLK (internal) CCI0A CCR0 TA0 Not used
VLO (internal) CCI0B Timer1_A1 CCI0B input
DVSS GND
DVCC VCC
P1.1 TA0.1 CCI1A CCR1 TA1 TA0.1
RTC (internal) CCI1B Timer1_A1 CCI1B input
DVSS GND
DVCC VCC
P1.2 TA0.2 CCI2A CCR2 TA2 TA0.2
N/A CCI2B Timer1_A1 INCLK
Timer1_A1 CCI2B input,
IR carrier input
DVSS GND
DVCC VCC
Table 9-13 Timer0_A1 Signal Connections
PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P1.6 TA1CLK TACLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
Timer0_A3 CCR2B output (internal) INCLK
N/A CCI0A CCR0 TA0 Not used
Timer0_A3 CCR0B output (internal) CCI0B Not used
DVSS GND
DVCC VCC
P1.5 TA1.1 CCI1A CCR1 TA1 TA1.1
Timer0_A3 CCR1B output (internal) CCI1B To ADC trigger
DVSS GND
DVCC VCC
P1.4 TA1.2 CCI2A CCR2 TA2 TA1.2
Timer0_A3 CCR2B output (internal) CCI2B IR coding input
DVSS GND
DVCC VCC
GUID-ADB9A408-EEF8-49B4-A345-91F864E5E48D-low.gif Figure 9-2 TA0 and TA1 Signal Connections
Table 9-14 Timer2_A3 and Timer3_A3 Signal Connections
PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P3.4 TA2CLK TACLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
VLO (internal) INCLK
P2.3 TA2.0 CCI0A CCR0 TA0 TA2.0
VLO (internal) CCI0B Timer3_A3 CCI0B input
DVSS GND
DVCC VCC
P3.3 TA2.1 CCI1A CCR1 TA1 TA2.1
RTC (internal) CCI1B Timer3_A3 CCI1B input
DVSS GND
DVCC VCC
P3.0 TA2.2 CCI2A CCR2 TA2 TA2.2
N/A CCI2B Timer3_A3 CCI2B input
DVSS GND
DVCC VCC
P4.2 TA3CLK TACLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
Timer2_A3 CCR2B output (internal) INCLK
P4.1 TA3.0 CCI0A CCR0 TA0 TA3.0
Timer2_A3 CCR0B output (internal) CCI0B Timer3_B0 CCI0B input
DVSS GND
DVCC VCC
P4.0 TA3.1 CCI1A CCR1 TA1 TA3.1
Timer2_A3 CCR1B output (internal) CCI1B Timer3_B0 CCI1B input
DVSS GND
DVCC VCC
P3.7 TA3.2 CCI2A CCR2 TA2 TA3.2
Timer2_A3 CCR2B output (internal) CCI2B Timer3_B0 CCI2B input
DVSS GND
DVCC VCC
Table 9-15 Timer0_B7 Signal Connections
PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P6.1 TB0CLK TBCLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
N/A INCLK
P6.2 TB0.0 CCI0A CCR0 TB0 TB0.0
Timer3_A3 CCI0B input (internal) CCI0B
DVSS GND
DVCC VCC
P4.7 TB0.1 CCI1A CCR1 TB1 TB0.1
Timer3_A3 CCI1B input (internal) CCI1B
DVSS GND
DVCC VCC
P5.0 TB0.2 CCI2A CCR2 TB2 TB0.2
Timer3_A3 CCI2B input (internal) CCI2B
DVSS GND
DVCC VCC
P5.1 TB0.3 CCI1A CCR3 TB3 TB0.3
N/A CCI1B
DVSS GND
DVCC VCC
P5.2 TB0.4 CCI1A CCR4 TB4 TB0.4
N/A CCI1B
DVSS GND
DVCC VCC
P4.3 TB0.5 CCI1A CCR5 TB5 TB0.5
N/A CCI1B
DVSS GND
DVCC VCC
P4.4 TB0.6 CCI1A CCR6 TB6 TB0.6
N/A CCI1B
DVSS GND
DVCC VCC
GUID-186A6A16-4979-4BEF-987C-0EC1A034C6E3-low.gif Figure 9-3 TA2, TA3 and TB0 Signal Connections
Table 9-16 TA2 and TA3 Pin Configurations of Remap Functionality
TA2 PIN (PxSEL Selection) DEVICE INPUT/OUTPUT SIGNAL
P3.4(1) TA2CLK
P2.3(1) TA2.0
P3.3(1) TA2.1
P3.0(1) TA2.2
PIN (PxSEL Selection) DEVICE INPUT/OUTPUT SIGNAL
P5.5(2) TA2CLK
P5.6(2) TA2.0
P5.7(2) TA2.1
P6.0(2) TA2.2
TA3 PIN (PxSEL Selection) DEVICE INPUT/OUTPUT SIGNAL
P4.2(1) TA3CLK
P4.1(1) TA3.0
P4.0(1) TA3.1
P3.7(1) TA3.2
PIN (PxSEL Selection) DEVICE INPUT/OUTPUT SIGNAL
P5.4(2) TA3CLK
P5.3(2) TA3.0
P4.6(2) TA3.1
P4.5(2) TA3.2
(1) This is the default functionality that can be remapped by the TAxRMP bit of the SYSCFG3 register. Only one selected port is valid at any time.
(2) This is the remapped functionality controlled by the TAxRMP bit of the SYSCFG3 register. Only one selected port is valid at any time.

The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS configuration register 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the MP430FR4xx and MP430FR2xx Family User's Guide.

The Timer_B module feature the function to put Timer_B all outputs into a high impedance state when the selected source is triggered. The source can be selected from external pin or internal of the device, it is controlled by TBxTRG in SYS. For more information, see the SYS chapter in the MP430FR4xx and MP430FR2xx Family User's Guide.

Table 9-17 lists the Timer_B high-impedance trigger source selections.

Table 9-17 TB0OUTH Selection
TB0TRGSEL TB0OUTH TRIGGER SOURCE SELECTION Timer_B PAD OUTPUT HIGH IMPEDANCE
TB0TRGSEL = 0 eCOMP0 output (internal) P6.2, P4.7, P5.0, P5.1, P5.2, P4.3, P4.4
TB0TRGSEL= 1 P3.5