JAJSG11F October   2014  – December 2021 MSP430FR4131 , MSP430FR4132 , MSP430FR4133

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
    3. 7.3 Pin Multiplexing
    4. 7.4 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 REFO
        4. 8.12.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.12.3.5 Module Oscillator Clock (MODCLK)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Digital I/O Typical Characteristics
      5. 8.12.5  Timer_A
        1. 8.12.5.1 Timer_A
      6. 8.12.6  eUSCI
        1. 8.12.6.1 eUSCI (UART Mode) Operating Frequency
        2. 8.12.6.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.12.6.3 eUSCI (SPI Master Mode) Operating Frequency
        4. 8.12.6.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.12.6.5 eUSCI (SPI Slave Mode) Switching Characteristics
        6. 8.12.6.6 eUSCI (I2C Mode) Switching Characteristics
      7. 8.12.7  ADC
        1. 8.12.7.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.7.2 ADC, 10-Bit Timing Parameters
        3. 8.12.7.3 ADC, 10-Bit Linearity Parameters
      8. 8.12.8  LCD Controller
        1. 8.12.8.1 LCD Recommended Operating Conditions
      9. 8.12.9  FRAM
        1. 8.12.9.1 FRAM
      10. 8.12.10 Emulation and Debug
        1. 8.12.10.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Bootloader (BSL)
    5. 9.5  JTAG Standard Interface
    6. 9.6  Spy-Bi-Wire Interface (SBW)
    7. 9.7  FRAM
    8. 9.8  Memory Protection
    9. 9.9  Peripherals
      1. 9.9.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 9.9.2  Clock System (CS) and Clock Distribution
      3. 9.9.3  General-Purpose Input/Output Port (I/O)
      4. 9.9.4  Watchdog Timer (WDT)
      5. 9.9.5  System Module (SYS)
      6. 9.9.6  Cyclic Redundancy Check (CRC)
      7. 9.9.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.9.8  Timers (Timer0_A3, Timer1_A3)
      9. 9.9.9  Real-Time Clock (RTC) Counter
      10. 9.9.10 10-Bit Analog Digital Converter (ADC)
      11. 9.9.11 Liquid Crystal Display (LCD)
      12. 9.9.12 Embedded Emulation Module (EEM)
      13. 9.9.13 Input/Output Schematics
        1. 9.9.13.1  Port P1 Input/Output With Schmitt Trigger
        2. 9.9.13.2  Port P2 Input/Output With Schmitt Trigger
        3. 9.9.13.3  Port P3 Input/Output With Schmitt Trigger
        4. 9.9.13.4  Port P4.0 Input/Output With Schmitt Trigger
        5. 9.9.13.5  Port P4.1 and P4.2 Input/Output With Schmitt Trigger
        6. 9.9.13.6  Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
        7. 9.9.13.7  Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
        8. 9.9.13.8  Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
        9. 9.9.13.9  Port P6 Input/Output With Schmitt Trigger
        10. 9.9.13.10 Port P7 Input/Output With Schmitt Trigger
        11. 9.9.13.11 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
        12. 9.9.13.12 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
    10. 9.10 Device Descriptors (TLV)
    11. 9.11 Memory
      1. 9.11.1 Peripheral File Map
    12. 9.12 Identification
      1. 9.12.1 Revision Identification
      2. 9.12.2 Device Identification
      3. 9.12.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
      2. 10.2.2 LCD_E Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
      3. 10.2.3 Timer
        1. 10.2.3.1 Generate Accurate PWM Using Internal Oscillator
    3. 10.3 Typical Applications
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.11.1 Peripheral File Map

Table 9-29 shows the base address and the memory size of the registers of each peripheral, and Table 9-30 through Table 9-49 show all of the available registers for each peripheral and their address offsets.

Table 9-29 Peripherals Summary
MODULE NAMEBASE ADDRESSSIZE
Special Functions (see Table 9-30)0100h0010h
PMM (see Table 9-31)0120h0020h
SYS (see Table 9-32)0140h0030h
CS (see Table 9-33)0180h0020h
FRAM (see Table 9-34)01A0h0010h
CRC (see Table 9-35)01C0h0008h
WDT (see Table 9-36)01CCh0002h
Port P1, P2 (see Table 9-37)0200h0020h
Port P3, P4 (see Table 9-38)0220h0020h
Port P5, P6 (see Table 9-39)0240h0020h
Port P7, P8 (see Table 9-40)0260h0020h
Capacitive Touch I/O (see Table 9-41)02E0h0010h
Timer0_A3 (see Table 9-42)0300h0030h
Timer1_A3 (see Table 9-43)0340h0030h
RTC (see Table 9-44)03C0h0010h
eUSCI_A0 (see Table 9-45)0500h0020h
eUSCI_B0 (see Table 9-46)0540h0030h
LCD (see Table 9-47)0600h0060h
Backup Memory (see Table 9-48)0660h0020h
ADC (see Table 9-49)0700h0040h
Table 9-30 Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTIONREGISTEROFFSET
SFR interrupt enableSFRIE100h
SFR interrupt flagSFRIFG102h
SFR reset pin controlSFRRPCR04h
Table 9-31 PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTIONREGISTEROFFSET
PMM control 0PMMCTL000h
PMM control 1PMMCTL102h
PMM control 2PMMCTL204h
PMM interrupt flagsPMMIFG0Ah
PM5 Control 0PM5CTL010h
Table 9-32 SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTIONREGISTEROFFSET
System controlSYSCTL00h
Bootloader configuration areaSYSBSLC02h
JTAG mailbox controlSYSJMBC06h
JTAG mailbox input 0SYSJMBI008h
JTAG mailbox input 1SYSJMBI10Ah
JTAG mailbox output 0SYSJMBO00Ch
JTAG mailbox output 1SYSJMBO10Eh
Bus Error vector generatorSYSBERRIV18h
User NMI vector generatorSYSUNIV1Ah
System NMI vector generatorSYSSNIV1Ch
Reset vector generatorSYSRSTIV1Eh
System configuration 0SYSCFG020h
System configuration 1SYSCFG122h
System configuration 2SYSCFG224h
Table 9-33 CS Registers (Base Address: 0180h)
REGISTER DESCRIPTIONREGISTEROFFSET
CS control register 0CSCTL000h
CS control register 1CSCTL102h
CS control register 2CSCTL204h
CS control register 3CSCTL306h
CS control register 4CSCTL408h
CS control register 5CSCTL50Ah
CS control register 6CSCTL60Ch
CS control register 7CSCTL70Eh
CS control register 8CSCTL810h
Table 9-34 FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTIONREGISTEROFFSET
FRAM control 0FRCTL000h
General control 0GCCTL004h
General control 1GCCTL106h
Table 9-35 CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTIONREGISTEROFFSET
CRC data inputCRC16DI00h
CRC data input reverse byteCRCDIRB02h
CRC initialization and resultCRCINIRES04h
CRC result reverse byteCRCRESR06h
Table 9-36 WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTIONREGISTEROFFSET
Watchdog timer controlWDTCTL00h
Table 9-37 Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port P1 inputP1IN00h
Port P1 outputP1OUT02h
Port P1 directionP1DIR04h
Port P1 pulling register enableP1REN06h
Port P1 selection 0P1SEL00Ah
Port P1 interrupt vector wordP1IV0Eh
Port P1 interrupt edge selectP1IES18h
Port P1 interrupt enableP1IE1Ah
Port P1 interrupt flagP1IFG1Ch
Port P2 inputP2IN01h
Port P2 outputP2OUT03h
Port P2 directionP2DIR05h
Port P2 pulling register enableP2REN07h
Port P2 selection 0(1)P2SEL00Bh
Port P2 interrupt vector wordP2IV1Eh
Port P2 interrupt edge selectP2IES19h
Port P2 interrupt enableP2IE1Bh
Port P2 interrupt flagP2IFG1Dh
(1) Port P2 selection register does not feature any valid bits. P2SEL0 presents for 16-bit Port A operation with P1SEL0.
Table 9-38 Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port P3 inputP3IN00h
Port P3 outputP3OUT02h
Port P3 directionP3DIR04h
Port P3 pulling register enableP3REN06h
Port P3 selection 0(1)P3SEL00Ah
Port P4 inputP4IN01h
Port P4 outputP4OUT03h
Port P4 directionP4DIR05h
Port P4 pulling register enableP4REN07h
Port P4 selection 0P4SEL00Bh
(1) Port P3 selection register does not feature any valid bits. P3SEL0 presents for 16-bit Port B operation with P4SEL0.
Table 9-39 Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port P5 inputP5IN00h
Port P5 outputP5OUT02h
Port P5 directionP5DIR04h
Port P5 pulling register enableP5REN06h
Port P5 selection 0P5SEL00Ah
Port P6 inputP6IN01h
Port P6 outputP6OUT03h
Port P6 directionP6DIR05h
Port P6 pulling register enableP6REN07h
Port P6 selection 0(1)P6SEL00Bh
(1) Port P6 selection register does not feature any valid bits. P6SEL0 presents for 16-bit Port C operation with P5SEL0.
Table 9-40 Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port P7 inputP7IN00h
Port P7 outputP7OUT02h
Port P7 directionP7DIR04h
Port P7 pulling register enableP7REN06h
Port P7 selection 0(1)P7SEL00Ah
Port P8 inputP8IN01h
Port P8 outputP8OUT03h
Port P8 directionP8DIR05h
Port P8 pulling register enableP8REN07h
Port P8 selection 0P8SEL00Bh
(1) Port P7 selection register does not feature any valid bits. P7SEL0 presents for 16-bit Port D operation with P8SEL0.
Table 9-41 Capacitive Touch IO Registers (Base Address: 02E0h)
REGISTER DESCRIPTIONREGISTEROFFSET
Capacitive Touch IO 0 controlCAPTIO0CTL0Eh
Table 9-42 Timer0_A3 Registers (Base Address: 0300h)
REGISTER DESCRIPTIONREGISTEROFFSET
TA0 controlTA0CTL00h
Capture/compare control 0TA0CCTL002h
Capture/compare control 1TA0CCTL104h
Capture/compare control 2TA0CCTL206h
TA0 counter registerTA0R10h
Capture/compare register 0TA0CCR012h
Capture/compare register 1TA0CCR114h
Capture/compare register 2TA0CCR216h
TA0 expansion register 0TA0EX020h
TA0 interrupt vectorTA0IV2Eh
Table 9-43 Timer1_A3 Registers (Base Address: 0340h)
REGISTER DESCRIPTIONREGISTEROFFSET
TA1 controlTA1CTL00h
Capture/compare control 0TA1CCTL002h
Capture/compare control 1TA1CCTL104h
Capture/compare control 2TA1CCTL206h
TA1 counter registerTA1R10h
Capture/compare register 0TA1CCR012h
Capture/compare register 1TA1CCR114h
Capture/compare register 2TA1CCR216h
TA1 expansion register 0TA1EX020h
TA1 interrupt vectorTA1IV2Eh
Table 9-44 RTC Registers (Base Address: 03C0h)
REGISTER DESCRIPTIONREGISTEROFFSET
RTC controlRTCCTL00h
RTC interrupt vectorRTCIV04h
RTC moduloRTCMOD08h
RTC counterRTCCNT0Ch
Table 9-45 eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTIONREGISTEROFFSET
eUSCI_A control word 0UCA0CTLW000h
eUSCI_A control word 1UCA0CTLW102h
eUSCI_A control rate 0UCA0BR006h
eUSCI_A control rate 1UCA0BR107h
eUSCI_A modulation controlUCA0MCTLW08h
eUSCI_A statusUCA0STAT0Ah
eUSCI_A receive bufferUCA0RXBUF0Ch
eUSCI_A transmit bufferUCA0TXBUF0Eh
eUSCI_A LIN controlUCA0ABCTL10h
eUSCI_A IrDA transmit controllUCA0IRTCTL12h
eUSCI_A IrDA receive controlIUCA0IRRCTL13h
eUSCI_A interrupt enableUCA0IE1Ah
eUSCI_A interrupt flagsUCA0IFG1Ch
eUSCI_A interrupt vector wordUCA0IV1Eh
Table 9-46 eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTIONREGISTEROFFSET
eUSCI_B control word 0UCB0CTLW000h
eUSCI_B control word 1UCB0CTLW102h
eUSCI_B bit rate 0UCB0BR006h
eUSCI_B bit rate 1UCB0BR107h
eUSCI_B status wordUCB0STATW08h
eUSCI_B byte counter thresholdUCB0TBCNT0Ah
eUSCI_B receive bufferUCB0RXBUF0Ch
eUSCI_B transmit bufferUCB0TXBUF0Eh
eUSCI_B I2C own address 0UCB0I2COA014h
eUSCI_B I2C own address 1UCB0I2COA116h
eUSCI_B I2C own address 2UCB0I2COA218h
eUSCI_B I2C own address 3UCB0I2COA31Ah
eUSCI_B receive addressUCB0ADDRX1Ch
eUSCI_B address maskUCB0ADDMASK1Eh
eUSCI_B I2C slave addressUCB0I2CSA20h
eUSCI_B interrupt enableUCB0IE2Ah
eUSCI_B interrupt flagsUCB0IFG2Ch
eUSCI_B interrupt vector wordUCB0IV2Eh
Table 9-47 LCD Registers (Base Address: 0600h)
REGISTER DESCRIPTIONREGISTEROFFSET
LCD control register 0LCDCTL000h
LCD control register 1LCDCTL102h
LCD blink control registerLCDBLKCTL04h
LCD memory control registerLCDMEMCTL06h
LCD voltage control registerLCDVCTL08h
LCD port control 0LCDPCTL00Ah
LCD port control 1LCDPCTL10Ch
LCD port control 2LCDPCTL20Eh
LCD COM/SEG select registerLCDCSS014h
LCD COM/SEG select registerLCDCSS116h
LCD COM/SEG select registerLCDCSS218h
LCD interrupt vectorLCDIV1Eh
Display memory Static and 2 to 4 mux modes
LCD memory 0LCDM020h
LCD memory 1LCDM121h
LCD memory 2LCDM222h
   ⋮⋮⋮
LCD memory 19LCDM1933h
Reserved(1)34h
   ⋮⋮⋮
Reserved(1)3Fh
Blinking memory for Static and 2 to 4 mux modes
LCD blinking memory 0LCDBM040h
LCD blinking memory 1LCDBM141h
   ⋮⋮⋮
LCD blinking memory 19LCDBM1953h
Reserved(1)54h
   ⋮⋮⋮
Reserved(1)5Fh
Display memory for 5 to 8 mux modes
LCD memory 0LCDM020h
LCD memory 1LCDM121h
LCD memory 2LCDM222h
   ⋮⋮⋮
LCD memory 39LCDM3947h
Reserved(2)48h
   ⋮⋮⋮
Reserved(2)5Fh
(1) In static and 2-mux to 4-mux modes, LCD memory and blink memory 40 to 63 are not physically implemented.
(2) In 5-mux to 8-mux modes, LCD memory and blink memory 40 to 63 are not physically implemented.
Table 9-48 Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTIONREGISTEROFFSET
Backup memory 0BAKMEM000h
Backup memory 1BAKMEM102h
Backup memory 2BAKMEM204h
Backup memory 3BAKMEM306h
Backup memory 4BAKMEM408h
Backup memory 5BAKMEM50Ah
Backup memory 6BAKMEM60Ch
Backup memory 7BAKMEM70Eh
Backup memory 8BAKMEM810h
Backup memory 9BAKMEM912h
Backup memory 10BAKMEM1014h
Backup memory 11BAKMEM1116h
Backup memory 12BAKMEM1218h
Backup memory 13BAKMEM131Ah
Backup memory 14BAKMEM141Ch
Backup memory 15BAKMEM151Eh
Table 9-49 ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTIONREGISTEROFFSET
ADC control register 0ADCCTL000h
ADC control register 1ADCCTL102h
ADC control register 2ADCCTL204h
ADC window comparator low thresholdADCLO06h
ADC window comparator high thresholdADCHI08h
ADC memory control register 0ADCMCTL00Ah
ADC conversion memory registerADCMEM012h
ADC interrupt enableADCIE1Ah
ADC interrupt flagsADCIFG1Ch
ADC interrupt vector wordADCIV1Eh