JAJSG11F October   2014  – December 2021 MSP430FR4131 , MSP430FR4132 , MSP430FR4133

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
    3. 7.3 Pin Multiplexing
    4. 7.4 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 REFO
        4. 8.12.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.12.3.5 Module Oscillator Clock (MODCLK)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Digital I/O Typical Characteristics
      5. 8.12.5  Timer_A
        1. 8.12.5.1 Timer_A
      6. 8.12.6  eUSCI
        1. 8.12.6.1 eUSCI (UART Mode) Operating Frequency
        2. 8.12.6.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.12.6.3 eUSCI (SPI Master Mode) Operating Frequency
        4. 8.12.6.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.12.6.5 eUSCI (SPI Slave Mode) Switching Characteristics
        6. 8.12.6.6 eUSCI (I2C Mode) Switching Characteristics
      7. 8.12.7  ADC
        1. 8.12.7.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.7.2 ADC, 10-Bit Timing Parameters
        3. 8.12.7.3 ADC, 10-Bit Linearity Parameters
      8. 8.12.8  LCD Controller
        1. 8.12.8.1 LCD Recommended Operating Conditions
      9. 8.12.9  FRAM
        1. 8.12.9.1 FRAM
      10. 8.12.10 Emulation and Debug
        1. 8.12.10.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Bootloader (BSL)
    5. 9.5  JTAG Standard Interface
    6. 9.6  Spy-Bi-Wire Interface (SBW)
    7. 9.7  FRAM
    8. 9.8  Memory Protection
    9. 9.9  Peripherals
      1. 9.9.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 9.9.2  Clock System (CS) and Clock Distribution
      3. 9.9.3  General-Purpose Input/Output Port (I/O)
      4. 9.9.4  Watchdog Timer (WDT)
      5. 9.9.5  System Module (SYS)
      6. 9.9.6  Cyclic Redundancy Check (CRC)
      7. 9.9.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.9.8  Timers (Timer0_A3, Timer1_A3)
      9. 9.9.9  Real-Time Clock (RTC) Counter
      10. 9.9.10 10-Bit Analog Digital Converter (ADC)
      11. 9.9.11 Liquid Crystal Display (LCD)
      12. 9.9.12 Embedded Emulation Module (EEM)
      13. 9.9.13 Input/Output Schematics
        1. 9.9.13.1  Port P1 Input/Output With Schmitt Trigger
        2. 9.9.13.2  Port P2 Input/Output With Schmitt Trigger
        3. 9.9.13.3  Port P3 Input/Output With Schmitt Trigger
        4. 9.9.13.4  Port P4.0 Input/Output With Schmitt Trigger
        5. 9.9.13.5  Port P4.1 and P4.2 Input/Output With Schmitt Trigger
        6. 9.9.13.6  Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
        7. 9.9.13.7  Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
        8. 9.9.13.8  Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
        9. 9.9.13.9  Port P6 Input/Output With Schmitt Trigger
        10. 9.9.13.10 Port P7 Input/Output With Schmitt Trigger
        11. 9.9.13.11 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
        12. 9.9.13.12 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
    10. 9.10 Device Descriptors (TLV)
    11. 9.11 Memory
      1. 9.11.1 Peripheral File Map
    12. 9.12 Identification
      1. 9.12.1 Revision Identification
      2. 9.12.2 Device Identification
      3. 9.12.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
      2. 10.2.2 LCD_E Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
      3. 10.2.3 Timer
        1. 10.2.3.1 Generate Accurate PWM Using Internal Oscillator
    3. 10.3 Typical Applications
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.3.1 Generate Accurate PWM Using Internal Oscillator

Generating an accurate PWM signal using the device internal oscillator is an important feature for many cost-sensitive applications in which an external crystal is not desired. The MSP430FR4133 uses an on-chip 32-kHz RC oscillator (REFO) combined with the 16-MHz digitally controlled oscillator (DCO) with frequency-locked loop (FLL) to provide the clock source for the timer peripheral to generate the PWM. The REFO frequency may change across different temperatures. To achieve improved PWM accuracy, application software may periodically measure the device temperature and compute an appropriate timer capture/compare correction value to offset for REFO temperature drift. For more information on how to implement this algorithm refer to How to Achieve Higher Accuracy Timer with Internal Oscillator on MSP430 . Figure 10-6 shows the absolute value of a typical error percentage for a 44-kHz PWM signal over the temperature range.

The absolute value error percentages shown below can be interpreted as either positive or negative resulting in a slightly faster or slower PWM frequency.

GUID-20210803-CA0I-QDTB-BX8K-XHJBBK26NTQQ-low.png Figure 10-6 Calibrated 44-kHz Timer PWM Error Magnitude