JAJSGU5B January   2019  – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Current Consumption per Module
    12. 8.12 Thermal Resistance Characteristics
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. 8.13.1.1 Brownout and Device Reset Power Ramp Requirements
        2. 8.13.1.2 SVS
      2. 8.13.2  Reset Timing
        1. 8.13.2.1 Reset Input
      3. 8.13.3  Clock Specifications
        1. 8.13.3.1 Low-Frequency Crystal Oscillator, LFXT
        2. 8.13.3.2 High-Frequency Crystal Oscillator, HFXT
        3. 8.13.3.3 DCO
        4. 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.13.3.5 Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. 8.13.4.1 Wake-up Times From Low-Power Modes and Reset
        2. 8.13.4.2 Typical Wake-up Charges
        3. 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. 8.13.5.1 Digital Inputs
        2. 8.13.5.2 Digital Outputs
        3. 8.13.5.3 Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. 8.13.6.1 Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. 8.13.7.1 Timer_A
        2. 8.13.7.2 Timer_B
      8. 8.13.8  eUSCI
        1. 8.13.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
        6. 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
        7. 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
        8. 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
        9. 8.13.8.9 eUSCI (SPI Slave Mode) Timing Diagrams
      9. 8.13.9  Segment LCD Controller
        1. 8.13.9.1 LCD_C Recommended Operating Conditions
        2. 8.13.9.2 LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
        2. 8.13.10.2 12-Bit ADC, Timing Parameters
        3. 8.13.10.3 12-Bit ADC, Linearity Parameters
        4. 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
        5. 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 8.13.10.7 12-Bit ADC, External Reference
        8. 8.13.10.8 Temperature Sensor Typical Characteristics
      11. 8.13.11 Reference
        1. 8.13.11.1 REF, Built-In Reference
      12. 8.13.12 Comparator
        1. 8.13.12.1 Comparator_E
      13. 8.13.13 FRAM
        1. 8.13.13.1 FRAM Memory
      14. 8.13.14 USS
        1. 8.13.14.1 USS Recommended Operating Conditions
        2. 8.13.14.2 USS LDO
        3. 8.13.14.3 USSXTAL
        4. 8.13.14.4 USS HSPLL
        5. 8.13.14.5 USS SDHS
        6. 8.13.14.6 USS PHY Output Stage
        7. 8.13.14.7 USS PHY Input Stage, Multiplexer
        8. 8.13.14.8 USS_PGA
        9. 8.13.14.9 USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. 8.13.15.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS_A)
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Measurement Test Interface (MTIF)
      7. 9.13.7  Watchdog Timer (WDT_A)
      8. 9.13.8  System Module (SYS)
      9. 9.13.9  DMA Controller
      10. 9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 9.13.11 TA0, TA1, and TA4
      12. 9.13.12 TA2 and TA3
      13. 9.13.13 TB0
      14. 9.13.14 ADC12_B
      15. 9.13.15 USS_A
      16. 9.13.16 Comparator_E
      17. 9.13.17 CRC16
      18. 9.13.18 CRC32
      19. 9.13.19 AES256 Accelerator
      20. 9.13.20 True Random Seed
      21. 9.13.21 Shared Reference (REF)
      22. 9.13.22 LCD_C
      23. 9.13.23 Embedded Emulation
        1. 9.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 9.13.23.2 EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.5) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.0 to P2.1) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P2 (P2.2 to P2.3) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P2 (P2.4 to P2.5) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P2 (P2.6 to P2.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P3 (P3.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P3 (P3.1) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P3 (P3.2) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P3 (P3.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P3 (P3.4 to P3.5) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P3 (P3.6 to P3.7) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P4 (P4.0) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P4 (P4.1 to P4.7) Input/Output With Schmitt Trigger
      17. 9.14.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      18. 9.14.18 Port P6 (P6.0) Input/Output With Schmitt Trigger
      19. 9.14.19 Port P6 (P6.1 to P6.2) Input/Output With Schmitt Trigger
      20. 9.14.20 Port P6 (P6.3) Input/Output With Schmitt Trigger
      21. 9.14.21 Port P6 (P6.4) Input/Output With Schmitt Trigger
      22. 9.14.22 Port P6 (P6.5 and P6.7) Input/Output With Schmitt Trigger
      23. 9.14.23 Port P7 (P7.0) Input/Output With Schmitt Trigger
      24. 9.14.24 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      25. 9.14.25 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      26. 9.14.26 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Detailed Design Procedure
        4. 10.2.1.4 Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
    9. 11.9 Export Control Notice
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3 Signal Descriptions

Section 7.3 describes the signals for all device variants and package options.

Table 7-2 Signal Descriptions
FUNCTION SIGNAL NAME PIN NO.(1) PIN TYPE(2) DESCRIPTION
80-PIN PN 64-PIN PM OR RGC
ADC A0 4 3 I ADC analog input A0
A1 5 4 I ADC analog input A1
A2 31 25 I ADC analog input A2
A3 32 26 I ADC analog input A3
– AVSS AVSS I ADC analog input A4
– AVSS AVSS I ADC analog input A5
– AVSS AVSS I ADC analog input A6
– AVSS AVSS I ADC analog input A7
A8 25 19 I ADC analog input A8
A9 26 20 I ADC analog input A9
– AVSS AVSS I ADC analog input A10
– AVSS AVSS I ADC analog input A11
– AVSS AVSS I ADC analog input A12
– AVSS AVSS I ADC analog input A13
A14 2 2 I ADC analog input A14
A15 3 – I ADC analog input A15
VREF+ 5 4 O Output of positive reference voltage
VREF- 4 3 O Output of negative reference voltage
VeREF+ 5 4 I Input for an external positive reference voltage to the ADC
VeREF- 4 3 I Input for an external negative reference voltage to the ADC
Clock ACLK 54, 66 45, 52 O ACLK output
HFXIN 10 9 I Input for high-frequency crystal oscillator HFXT
HFXOUT 11 10 O Output for high-frequency crystal oscillator HFXT
LFXIN 7 6 I Input for low-frequency crystal oscillator LFXT
LFXOUT 8 7 O Output of low-frequency crystal oscillator LFXT
MCLK 52, 64 43, 50 O MCLK output
SMCLK 53, 65 44, 51 O SMCLK output
Comparator C0 4 3 I Comparator input C0
C1 5 4 I Comparator input C1
C2 31 25 I Comparator input C2
C3 32 26 I Comparator input C3
Not connected 4 3 I Comparator input C4
Not connected 4 3 I Comparator input C5
Not connected 4 3 I Comparator input C6
Not connected 4 3 I Comparator input C7
C8 25 19 I Comparator input C8
C9 26 20 I Comparator input C9
C10 17 13 I Comparator input C10
C11 18 14 I Comparator input C11
C12 19 15 I Comparator input C12
C13 20 16 I Comparator input C13
C14 2 2 I Comparator input C14
C15 3 – I Comparator input C15
COUT 2, 51, 66 2, 42, 52 O Comparator output
DMA DMAE0 17, 42, 65 13, 51 I External DMA trigger
Debug SBWTCK 15 11 I Spy-Bi-Wire input clock
SBWTDIO 16 12 I/O Spy-Bi-Wire data input/output
SRCPUOFF 20 16 O Low-power debug: CPU Status register bit CPUOFF
SROSCOFF 19 15 O Low-power debug: CPU Status register bit OSCOFF
SRSCG0 18 14 O Low-power debug: CPU Status register bit SCG0
SRSCG1 17 13 O Low-power debug: CPU Status register bit SCG1
TCK 20 16 I Test clock
TCLK 18 14 I Test clock input
TDI 18 14 I Test data input
TDO 17 13 O Test data output port
TEST 15 11 I Test mode pin – select digital I/O on JTAG pins
TMS 19 15 I Test mode select
GPIO, P1 P1.0 4 3 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.1 5 4 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.2 25 19 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.3 26 20 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.4 31 25 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.5 32 26 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.6 29 23 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.7 30 24 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO, P2 P2.0 27 21 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.1 28 22 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.2 2 2 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.3 3 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.4 12 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.5 23 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.6 13 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.7 14 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO, P3 P3.0 24 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.1 33 27 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.2 63 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.3 64 50 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.4 65 51 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.5 66 52 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.6 75 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.7 76 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO, P4 P4.0 34 28 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.1 35 29 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.2 36 30 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.3 37 31 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.4 38 32 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.5 39 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.6 40 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.7 42 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO, P5 P5.0 43 34 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.1 44 35 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.2 45 36 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.3 46 37 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.4 47 38 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.5 48 39 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.6 49 40 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.7 50 41 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO, P6 P6.0 51 42 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.1 56 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.2 57 47 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.3 60 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.4 52 43 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.5 53 44 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.6 54 45 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.7 62 – I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO, P7 P7.0 55 46 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO, PJ PJ.0 17 13 I/O General-purpose digital I/O
PJ.1 18 14 I/O General-purpose digital I/O
PJ.2 19 15 I/O General-purpose digital I/O
PJ.3 20 16 I/O General-purpose digital I/O
PJ.4 7 6 I/O General-purpose digital I/O
PJ.5 8 7 I/O General-purpose digital I/O
PJ.6 10 9 I/O General-purpose digital I/O
PJ.7 11 10 I/O General-purpose digital I/O
I2C UCB0SCL 30 24 I/O I2C clock – eUSCI_B0 I2C mode
UCB0SDA 29 23 I/O I2C data – eUSCI_B0 I2C mode
UCB1SCL 49, 76 40 I/O I2C clock – eUSCI_B1 I2C mode
UCB1SDA 48, 75 39 I/O I2C data – eUSCI_B1 I2C mode
LCD COM0 52 – O LCD common output COM0 for LCD backplane
COM1 53 – O LCD common output COM1 for LCD backplane
COM2 54 – O LCD common output COM2 for LCD backplane
COM3 66 – O LCD common output COM3 for LCD backplane
COM4 62 – O LCD common output COM4 for LCD backplane
COM5 63 – O LCD common output COM5 for LCD backplane
COM6 65 – O LCD common output COM6 for LCD backplane
COM7 60 – O LCD common output COM7 for LCD backplane
LCDCAP 61 – I/O LCD capacitor connection
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
LCDREF 57 – I External reference voltage input for regulated LCD voltage
R03 56 – I/O Input/output port of lowest analog LCD voltage (V5)
R13 57 – I/O Input/output port of third most positive analog LCD voltage (V3 or V4)
R23 60 – I/O Input/output port of second most positive analog LCD voltage (V2)
R33 61 – I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
LCD S0 51 – O LCD segment output 0
S1 50 – O LCD segment output 1
S2 49 – O LCD segment output 2
S3 48 – O LCD segment output 3
S4 47 – O LCD segment output 4
S5 46 – O LCD segment output 5
S6 45 – O LCD segment output 6
S7 44 – O LCD segment output 7
S8 43 – O LCD segment output 8
S9 42 – O LCD segment output 9
S10 40 – O LCD segment output 10
S11 39 – O LCD segment output 11
S12 38 – O LCD segment output 12
S13 37 – O LCD segment output 13
S14 36 – O LCD segment output 14
S15 35 – O LCD segment output 15
S16 30 – O LCD segment output 16
S17 29 – O LCD segment output 17
S18 28 – O LCD segment output 18
S19 27 – O LCD segment output 19
S20 24 – O LCD segment output 20
S21 23 – O LCD segment output 21
S22 14 – O LCD segment output 22
S23 13 – O LCD segment output 23
S24 12 – O LCD segment output 24
S25 64 – O LCD segment output 25
S26 66 – O LCD segment output 26
S27 65 – O LCD segment output 27
S28 63 – O LCD segment output 28
S29 62 – O LCD segment output 29
S30 55 – O LCD segment output 30
S31 54 – O LCD segment output 31
S32 57 – O LCD segment output 32
S33 56 – O LCD segment output 33
S34 53 – O LCD segment output 34
S35 75 – O LCD segment output 35
S36 76 – O LCD segment output 36
MTIF MTIF_PIN_EN 34 28 I Meter test Interface pin enable
MTIF_OUT_IN 33 27 I/O Meter test Interface In/Out
Power AVCC1 1 1 P Analog power supply
AVSS1 80 64 P Analog ground supply
AVSS2 6 5 P Analog ground supply
AVSS3 9 8 P Analog ground supply
AVSS4 77 61 P Analog ground supply
DVCC1 22 18 P Digital power supply
DVCC3 59 49 P Digital power supply
DVSS1 21 17 P Digital ground supply
DVSS2 41 33 P Digital ground supply
DVSS3 58 48 P Digital ground supply
PVCC 70, 71 56, 57 P USS power supply
PVSS 69, 72 55, 58 P USS ground supply
RTC RTCCLK 34, 56 28 O RTC clock calibration output
SPI UCA0CLK 2, 35 2, 29 I/O Clock signal input – eUSCI_A0 SPI slave mode
Clock signal output – eUSCI_A0 SPI master mode
UCA0SIMO 13, 37 31 I/O Slave in/master out – eUSCI_A0 SPI mode
UCA0SOMI 14, 38 32 I/O Slave out/master in – eUSCI_A0 SPI mode
UCA0STE 3, 36 30 I/O Slave transmit enable – eUSCI_A0 SPI mode
UCA1CLK 4, 27 3, 21 I/O Clock signal input – eUSCI_A1 SPI slave mode
Clock signal output – eUSCI_A1 SPI master mode
UCA1SIMO 25 19 I/O Slave in/master out – eUSCI_A1 SPI mode
UCA1SOMI 26 20 I/O Slave out/master in – eUSCI_A1 SPI mode
UCA1STE 5, 28 4, 22 I/O Slave transmit enable – eUSCI_A1 SPI mode
UCA2CLK 45 36 I/O Clock signal input – eUSCI_A2 SPI slave mode
Clock signal output – eUSCI_A2 SPI master mode
UCA2SIMO 19, 43 34 I/O Slave in/master out – eUSCI_A2 SPI mode
UCA2SOMI 20, 44 35 I/O Slave out/master in – eUSCI_A2 SPI mode
UCA2STE 46 37 I/O Slave transmit enable – eUSCI_A2 SPI mode
UCA3CLK 30 24 I/O Clock signal input – eUSCI_A3 SPI slave mode
Clock signal output – eUSCI_A3 SPI master mode
UCA3SIMO 27, 36 21, 30 I/O Slave in/master out – eUSCI_A3 SPI mode
UCA3SOMI 28, 35 22, 29 I/O Slave out/master in – eUSCI_A3 SPI mode
UCA3STE 29 23 I/O Slave transmit enable – eUSCI_A3 SPI mode
UCB0CLK 32 26 I/O Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
UCB0SIMO 29 23 I/O Slave in/master out – eUSCI_B0 SPI mode
UCB0SOMI 30 24 I/O Slave out/master in – eUSCI_B0 SPI mode
UCB0STE 31 25 I/O Slave transmit enable – eUSCI_B0 SPI mode
UCB1CLK 47 38 I/O Clock signal input – eUSCI_B1 SPI slave mode
Clock signal output – eUSCI_B1 SPI master mode
UCB1SIMO 48, 75 39 I/O Slave in/master out – eUSCI_B1 SPI mode
UCB1SOMI 49, 76 40 I/O Slave out/master in – eUSCI_B1 SPI mode
UCB1STE 50 41 I/O Slave transmit enable – eUSCI_B1 SPI mode
System NMI 16 12 I Nonmaskable interrupt input
RST 16 12 I/O Reset input active low
Timer_A0 TA0.0 3 – I/O TA0 CCR0 capture: CCI0A input, compare: Out0
TA0.0 47 38 I/O TA0 CCR0 capture: CCI0B input, compare: Out0
TA0.1 62 – I/O TA0 CCR1 capture: CCI1A input, compare: Out1
TA0.2 50 41 I/O TA0 CCR2 capture: CCI2A input, compare: Out2
TA0.2 23 – O TA0 compare: Out2 enabled by COUT
TA0CLK 12, 39, 51 42 I TA0 input clock
Timer_A1 TA1.0 4 3 I/O TA1 CCR0 capture: CCI0A input, compare: Out0
TA1.0 55 46 I/O TA1 CCR0 capture: CCI0B input, compare: Out0
TA1.0 25 19 O TA1 CCR0 compare: Out0
TA1.1 63 – I/O TA1 CCR1 capture: CCI1A input, compare: Out1
TA1.1 26 20 O TA1 CCR1 compare: Out1
TA1.2 13 – I/O TA1 CCR2 capture: CCI2A input, compare: Out2
TA1.2 55 46 O TA1 CCR2 compare: Out2
TA1.2C 13 – O TA1 CCR2 compare: Out2 enabled by COUT
TA1CLK 12, 33, 39 27 I TA1 input clock
Timer_A4 TA4.0 5 4 I/O TA4 CCR0 capture: CCI0A input, compare: Out0
TA4.0 23 – I/O TA4 CCR0 capture: CCI0B input, compare: Out0
TA4.0 47 38 O TA4 CCR0 compare: Out0
TA4.1 14 – I/O TA4CCR1 capture: CCI1B input, compare: Out1
TA4.1 48 39 I/O TA4 CCR1 capture: CCI1A input, compare: Out1
TA4.1 34 28 O TA4 CCR1 compare: Out1
TA4.1C 14 – O TA4 CCR1 compare: Out1 enabled by COUT
TA4CLK 18, 40 14 I TA4 input clock
Timer_B0 TB0.0 43 34 I/O TB0 CCR0 capture: CCI0B input, compare: Out0
TB0.0 24 – I/O TB0 CCR0 capture: CCI0A input, compare: Out0
TB0.1 33 27 I/O TB0 CCR1 capture: CCI1A input, compare: Out1
TB0.1 44 35 O TB0 CCR1 compare: Out1
TB0.2 76 – I/O TB0 CCR2 capture: CCI2A input, compare: Out2
TB0.2 45 36 O TB0 CCR2 compare: Out2
TB0.3 46 37 I/O TB0 CCR3 capture: CCI3A input, compare: Out3
TB0.3 64 50 I/O TB0 CCR3 capture: CCI3B input, compare: Out3
TB0.4 31 25 I/O TB0 CCR4 capture: CCI4A input, compare: Out4
TB0.4 35 29 I/O TB0 CCR4 capture: CCI4B input, compare: Out4
TB0.5 32 26 I/O TB0 CCR5 capture: CCI5A input, compare: Out5
TB0.5 36 30 I/O TB0CCR5 capture: CCI5B input, compare: Out5
TB0.6 75 – I/O TB0 CCR6 capture: CCI6B input, compare: Out6
TB0.6 20 16 I/O TB0 CCR6 capture: CCI6A input, compare: Out6
TB0CLK 12, 40,57 47 I TB0 clock input
TB0OUTH 19, 49, 76 15 I Switch all PWM outputs high impedance input – TB0
UART UCA0RXD 14, 38 32 I Receive data – eUSCI_A0 UART mode
UCA0TXD 13, 37 31 O Transmit data – eUSCI_A0 UART mode
UCA1RXD 26 20 I Receive data – eUSCI_A1 UART mode
UCA1TXD 25 19 O Transmit data – eUSCI_A1 UART mode
UCA2RXD 20, 44 16, 35 I Receive data – eUSCI_A2 UART mode
UCA2TXD 19, 43 15, 34 O Transmit data – eUSCI_A2 UART mode
UCA3RXD 28, 35 22, 29 I Receive data – eUSCI_A3 UART mode
UCA3TXD 27, 36 21, 30 O Transmit data – eUSCI_A3 UART mode
USS_A USSTRG 30 24 I USS UUPS trigger
USSXTIN 78 62 I Input for an oscillator USSXT
USSXTOUT 79 63 O Output for an oscillator USSXT
USSXT_BOUT 75, 10 9 O Buffered output clock of USSXT
CH0_IN 74 60 I USS Channel 0 RX
CH0_OUT 73 59 I/O USS Channel 0 TX
CH1_IN 67 53 I USS Channel 1 RX
CH1_OUT 68 54 I/O USS Channel 1 TX
XPB0 55 46 O External bias output
XPB1 64 50 O External bias output
(1) N/A = not available
(2) I = input, O = output, P = power