SLASE35C May 2014 – December 2017 MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729
PRODUCTION DATA.
CAUTION | These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such as those experienced during reflow or hand soldering. See Absolute Maximum Ratings for more information. |
CAUTION | System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturb of data or code memory. See MSP430™ System-Level ESD Considerations for more information. |
The TI MSP430FR572x family of ultra-low-power microcontrollers consists of multiple devices that feature embedded FRAM nonvolatile memory, ultra-low-power 16-bit MSP430™ CPU, and different peripherals targeted for various applications. The architecture, FRAM, and peripherals, combined with seven low-power modes, are optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and reliability of flash, all at lower total power consumption. Peripherals include a 10-bit ADC, a 16-channel comparator with voltage reference generation and hysteresis capabilities, three enhanced serial channels capable of I2C, SPI, or UART protocols, an internal DMA, a hardware multiplier, an RTC, five 16-bit timers, and digital I/Os.
PART NUMBER | PACKAGE | BODY SIZE(2) |
---|---|---|
MSP430FR5729RHA | VQFN (40) | 6 mm × 6 mm |
MSP430FR5729DA | TSSOP (38) | 12.5 mm × 6.2 mm |
MSP430FR5728RGE | VQFN (24) | 4 mm × 4 mm |
MSP430FR5728PW | TSSOP (28) | 9.7 mm × 4.4 mm |
Figure 1-1 shows the functional block diagram for the MSP430FR5721, MSP430FR5725, and MSP430FR5729 devices in the RHA package. For the functional block diagrams for all device variants and package options, see Section 6.1.
Changes from October 1, 2016 to December 5, 2017
Table 3-1 summarizes the available family members.
DEVICE | FRAM (KB) |
SRAM (KB) |
SYSTEM CLOCK (MHz) |
ADC10_B | Comp_D | Timer_A(1) | Timer_B(2) | eUSCI | I/O | PACKAGE | |
---|---|---|---|---|---|---|---|---|---|---|---|
Channel A: UART, IrDA, SPI |
Channel B: SPI, I2C |
||||||||||
MSP430FR5729 | 16 | 1 | 8 | 12 ext, 2 int ch. | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5728 | 16 | 1 | 8 | 6 ext, 2 int ch. | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
8 ext, 2 int ch. | 12 ch. | 21 | PW | ||||||||
MSP430FR5727 | 16 | 1 | 8 | – | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5726 | 16 | 1 | 8 | – | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
12 ch. | 21 | PW | |||||||||
MSP430FR5725 | 8 | 1 | 8 | 12 ext, 2 int ch. | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5724 | 8 | 1 | 8 | 6 ext, 2 int ch. | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
8 ext, 2 int ch. | 12 ch. | 21 | PW | ||||||||
MSP430FR5723 | 8 | 1 | 8 | – | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5722 | 8 | 1 | 8 | – | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
12 ch. | 21 | PW | |||||||||
MSP430FR5721 | 4 | 1 | 8 | 12 ext, 2 int ch. | 16 ch. | 3, 3 | 3, 3, 3 | 2 | 1 | 32 | RHA |
30 | DA | ||||||||||
MSP430FR5720 | 4 | 1 | 8 | 6 ext, 2 int ch. | 10 ch. | 3, 3 | 3 | 1 | 1 | 17 | RGE |
8 ext, 2 int ch. | 12 ch. | 21 | PW |
For information about other devices in this family of products or related products, see the following links.
Figure 4-1 shows the pin diagram for the MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, and MSP430FR5729 devices in the 40-pin RHA package.
NOTE:
Exposed thermal pad connection to VSS recommended.Figure 4-2 shows the pin diagram for the MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, and MSP430FR5729 devices in the 38-pin DA package.
Figure 4-3 shows the pin diagram for the MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, and MSP430FR5728 devices in the 24-pin RGE package.
NOTE:
Exposed thermal pad connection to VSS recommended.Figure 4-4 shows the pin diagram for the MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, and MSP430FR5728 devices in the 28-pin PW package.
Table 4-1 describes the signals for all device variants and packages.
TERMINAL | I/O (1) | DESCRIPTION | ||||
---|---|---|---|---|---|---|
NAME | NO. | |||||
RHA | RGE | DA | PW | |||
P1.0/TA0.1/DMAE0/ RTCCLK/A0/CD0/VeREF- | 1 | 1 | 5 | 5 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA0 CCR1 capture: CCI1A input, compare: Out1 | ||||||
External DMA trigger | ||||||
RTC clock calibration output | ||||||
Analog input A0 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD0 | ||||||
External applied reference voltage (not available on devices without ADC) | ||||||
P1.1/TA0.2/TA1CLK/ CDOUT/A1/CD1/VeREF+ | 2 | 2 | 6 | 6 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA0 CCR2 capture: CCI2A input, compare: Out2 | ||||||
TA1 input clock | ||||||
Comparator_D output | ||||||
Analog input A1 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD1 | ||||||
Input for an external reference voltage to the ADC (not available on devices without ADC) | ||||||
P1.2/TA1.1/TA0CLK/ CDOUT/A2/CD2 | 3 | 3 | 7 | 7 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA1 CCR1 capture: CCI1A input, compare: Out1 | ||||||
TA0 input clock | ||||||
Comparator_D output | ||||||
Analog input A2 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD2 | ||||||
P3.0/A12/CD12 | 4 | N/A | 8 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
Analog input A12 – ADC (not available on devices without ADC or package options PW, RGE) | ||||||
Comparator_D input CD12 (not available on package options PW, RGE) | ||||||
P3.1/A13/CD13 | 5 | N/A | 9 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
Analog input A13 – ADC (not available on devices without ADC or package options PW, RGE) | ||||||
Comparator_D input CD13 (not available on package options PW, RGE) | ||||||
P3.2/A14/CD14 | 6 | N/A | 10 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
Analog input A14 – ADC (not available on devices without ADC or package options PW, RGE) | ||||||
Comparator_D input CD14 (not available on package options PW, RGE) | ||||||
P3.3/A15/CD15 | 7 | N/A | 11 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
Analog input A15 – ADC (not available on devices without ADC or package options PW, RGE) | ||||||
Comparator_D input CD15 (not available on package options PW, RGE) | ||||||
P1.3/TA1.2/UCB0STE/ A3/CD3 | 8 | 4 | 12 | 8 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TA1 CCR2 capture: CCI2A input, compare: Out2 | ||||||
Slave transmit enable – eUSCI_B0 SPI mode | ||||||
Analog input A3 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD3 | ||||||
P1.4/TB0.1/UCA0STE/ A4/CD4 | 9 | 5 | 13 | 9 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB0 CCR1 capture: CCI1A input, compare: Out1 | ||||||
Slave transmit enable – eUSCI_A0 SPI mode | ||||||
Analog input A4 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD4 | ||||||
P1.5/TB0.2/UCA0CLK/ A5/CD5 | 10 | 6 | 14 | 10 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB0 CCR2 capture: CCI2A input, compare: Out2 | ||||||
Clock signal input – eUSCI_A0 SPI slave mode, Clock signal output – eUSCI_A0 SPI master mode |
||||||
Analog input A5 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD5 | ||||||
PJ.0/TDO/TB0OUTH/ SMCLK/CD6 (4) | 11 | 7 | 15 | 11 | I/O | General-purpose digital I/O |
Test data output port | ||||||
Switch all PWM outputs high impedance input – TB0 | ||||||
SMCLK output | ||||||
Comparator_D input CD6 | ||||||
PJ.1/TDI/TCLK/TB1OUTH/ MCLK/CD7 (4) | 12 | 8 | 16 | 12 | I/O | General-purpose digital I/O |
Test data input or test clock input | ||||||
Switch all PWM outputs high impedance input – TB1 (not available on devices without TB1) | ||||||
MCLK output | ||||||
Comparator_D input CD7 | ||||||
PJ.2/TMS/TB2OUTH/ ACLK/CD8 (4) | 13 | 9 | 17 | 13 | I/O | General-purpose digital I/O |
Test mode select | ||||||
Switch all PWM outputs high impedance input – TB2 (not available on devices without TB2) | ||||||
ACLK output | ||||||
Comparator_D input CD8 | ||||||
PJ.3/TCK/CD9 (4) | 14 | 10 | 18 | 14 | I/O | General-purpose digital I/O |
Test clock | ||||||
Comparator_D input CD9 | ||||||
P4.0/TB2.0 | 15 | N/A | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on devices without TB2 or package options DA, PW, RGE) | ||||||
P4.1 | 16 | N/A | N/A | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options DA, PW, RGE) |
P2.5/TB0.0/UCA1TXD/ UCA1SIMO | 17 | N/A | 19 | 15 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB0 CCR0 capture: CCI0A input, compare: Out0 | ||||||
Transmit data – eUSCI_A1 UART mode, Slave in, master out – eUSCI_A1 SPI mode (not available on devices without UCSI_A1) | ||||||
P2.6/TB1.0/UCA1RXD/ UCA1SOMI | 18 | N/A | 20 | 16 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1) | ||||||
Receive data – eUSCI_A1 UART mode, Slave out, master in – eUSCI_A1 SPI mode (not available on devices without UCSI_A1) | ||||||
TEST/SBWTCK (4) (3) | 19 | 11 | 21 | 17 | I | Test mode pin – enable JTAG pins |
Spy-Bi-Wire input clock | ||||||
RST/NMI/SBWTDIO (4) (3) | 20 | 12 | 22 | 18 | I/O | Reset input active low |
Non-maskable interrupt input | ||||||
Spy-Bi-Wire data input/output | ||||||
P2.0/TB2.0/UCA0TXD/ UCA0SIMO/TB0CLK/ACLK (3) | 21 | 13 | 23 | 19 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB2) | ||||||
Transmit data – eUSCI_A0 UART mode | ||||||
Slave in, master out – eUSCI_A0 SPI mode | ||||||
TB0 clock input | ||||||
ACLK output | ||||||
P2.1/TB2.1/UCA0RXD/ UCA0SOMI/TB0.0 (3) | 22 | 14 | 24 | 20 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB2) | ||||||
Receive data – eUSCI_A0 UART mode | ||||||
Slave out, master in – eUSCI_A0 SPI mode | ||||||
TB0 CCR0 capture: CCI0A input, compare: Out0 | ||||||
P2.2/TB2.2/UCB0CLK/ TB1.0 | 23 | 15 | 25 | 21 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB2) | ||||||
Clock signal input – eUSCI_B0 SPI slave mode, Clock signal output – eUSCI_B0 SPI master mode |
||||||
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1) | ||||||
P3.4/TB1.1/TB2CLK/ SMCLK | 24 | N/A | 26 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB1) | ||||||
TB2 clock input (not available on devices without TB2 or package options PW, RGE) | ||||||
SMCLK output (not available on package options PW, RGE) | ||||||
P3.5/TB1.2/CDOUT | 25 | N/A | 27 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB1) | ||||||
Comparator_D output (not available on package options PW, RGE) | ||||||
P3.6/TB2.1/TB1CLK | 26 | N/A | 28 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB2) | ||||||
TB1 clock input (not available on devices without TB1 or package options PW, RGE) | ||||||
P3.7/TB2.2 | 27 | N/A | 29 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB2 or package options PW, RGE) | ||||||
P1.6/TB1.1/UCB0SIMO/ UCB0SDA/TA0.0 | 28 | 16 | 30 | 22 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB1) | ||||||
Slave in, master out – eUSCI_B0 SPI mode | ||||||
I2C data – eUSCI_B0 I2C mode | ||||||
TA0 CCR0 capture: CCI0A input, compare: Out0 | ||||||
P1.7/TB1.2/UCB0SOMI/ UCB0SCL/TA1.0 | 29 | 17 | 31 | 23 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 |
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB1) | ||||||
Slave out, master in – eUSCI_B0 SPI mode | ||||||
I2C clock – eUSCI_B0 I2C mode | ||||||
TA1 CCR0 capture: CCI0A input, compare: Out0 | ||||||
VCORE (2) | 30 | 18 | 32 | 24 | Regulated core power supply (internal use only, no external current loading) | |
DVSS | 31 | 19 | 33 | 25 | Digital ground supply | |
DVCC | 32 | 20 | 34 | 26 | Digital power supply | |
P2.7 | 33 | N/A | 35 | N/A | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) |
P2.3/TA0.0/UCA1STE/ A6/CD10 | 34 | N/A | 36 | 27 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options RGE) |
TA0 CCR0 capture: CCI0B input, compare: Out0 (not available on package options RGE) | ||||||
Slave transmit enable – eUSCI_A1 SPI mode (not available on devices without eUSCI_A1) | ||||||
Analog input A6 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD10 (not available on package options RGE) | ||||||
P2.4/TA1.0/UCA1CLK/ A7/CD11 | 35 | N/A | 37 | 28 | I/O | General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options RGE) |
TA1 CCR0 capture: CCI0B input, compare: Out0 (not available on package options RGE) | ||||||
Clock signal input – eUSCI_A1 SPI slave mode, Clock signal output – eUSCI_A1 SPI master mode (not available on devices without eUSCI_A1) | ||||||
Analog input A7 – ADC (not available on devices without ADC) | ||||||
Comparator_D input CD11 (not available on package options RGE) | ||||||
AVSS | 36 | N/A | 38 | N/A | Analog ground supply | |
PJ.4/XIN | 37 | 21 | 1 | 1 | I/O | General-purpose digital I/O |
Input terminal for crystal oscillator XT1 | ||||||
PJ.5/XOUT | 38 | 22 | 2 | 2 | I/O | General-purpose digital I/O |
Output terminal of crystal oscillator XT1 | ||||||
AVSS | 39 | 23 | 3 | 3 | Analog ground supply | |
AVCC | 40 | 24 | 4 | 4 | Analog power supply | |
QFN Pad | Pad | Pad | N/A | N/A | QFN package pad. Connection to VSS recommended. |
MIN | MAX | UNIT | |
---|---|---|---|
Voltage applied at VCC to VSS | –0.3 | 4.1 | V |
Voltage applied to any pin (excluding VCORE) (2) | –0.3 | VCC + 0.3 | V |
Diode current at any device pin | ±2 | mA | |
Maximum junction temperature, TJ | 95 | °C | |
Storage temperatureTstg(3) (4) (5) | –55 | 125 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) | ±250 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage during program execution and FRAM programming (AVCC = DVCC) (1) | 2.0 | 3.6 | V | ||
VSS | Supply voltage (AVSS = DVSS) | 0 | V | |||
TA | Operating free-air temperature | –40 | 85 | °C | ||
TJ | Operating junction temperature | –40 | 85 | °C | ||
CVCORE | Required capacitor at VCORE(2) | 470 | nF | |||
CVCC/ CVCORE | Capacitor ratio of VCC to VCORE | 10 | ||||
fSYSTEM | Processor frequency (maximum MCLK frequency)(3) | No FRAM wait states(4), 2 V ≤ VCC ≤ 3.6 V |
0 | 8.0 | MHz |
PARAMETER | EXECUTION MEMORY | VCC | Frequency (fMCLK = fSMCLK) | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|
1 MHz | 4 MHz | 8 MHz | |||||||
TYP | MAX | TYP | MAX | TYP | MAX | ||||
IAM, FRAM_UNI(5) | FRAM | 3 V | 0.27 | 0.58 | 1.0 | mA | |||
IAM,0%(6) | FRAM 0% cache hit ratio |
3 V | 0.42 | 0.73 | 1.2 | 1.6 | 2.2 | 2.8 | mA |
IAM,50%(6) (4) | FRAM 50% cache hit ratio |
3 V | 0.31 | 0.73 | 1.3 | mA | |||
IAM,66%(6) (4) | FRAM 66% cache hit ratio |
3 V | 0.27 | 0.58 | 1.0 | mA | |||
IAM,75%(6) (4) | FRAM 75% cache hit ratio |
3 V | 0.25 | 0.5 | 0.82 | mA | |||
IAM,100%(6) (4) | FRAM 100% cache hit ratio |
3 V | 0.2 | 0.43 | 0.3 | 0.55 | 0.42 | 0.8 | mA |
IAM, RAM(4) (7) | RAM | 3 V | 0.2 | 0.4 | 0.35 | 0.55 | 0.55 | 0.75 | mA |
PARAMETER | VCC | –40°C | 25°C | 60°C | 85°C | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|---|
TYP | MAX | TYP | MAX | TYP | MAX | TYP | MAX | ||||
ILPM0,1MHz | Low-power mode 0 (3) (12) | 2 V, 3 V |
166 | 175 | 190 | 225 | µA | ||||
LPM0,8MHz | Low-power mode 0 (4) (12) | 2 V, 3 V |
170 | 177 | 244 | 195 | 225 | 360 | µA | ||
LPM0,24MHz | Low-power mode 0 (5) (12) | 2 V, 3 V |
274 | 285 | 340 | 315 | 340 | 455 | µA | ||
ILPM2 | Low-power mode 2 (6) (13) | 2 V, 3 V |
56 | 61 | 80 | 75 | 110 | 210 | µA | ||
ILPM3,XT1LF | Low-power mode 3, crystal mode (7) (13) | 2 V, 3 V |
3.4 | 6.4 | 15 | 18 | 48 | 150 | µA | ||
ILPM3,VLO | Low-power mode 3, VLO mode (8) (13) | 2 V, 3 V |
3.3 | 6.3 | 15 | 18 | 48 | 150 | µA | ||
ILPM4 | Low-power mode 4 (9) (13) | 2 V, 3 V |
2.9 | 5.9 | 15 | 18 | 48 | 150 | µA | ||
ILPM3.5 | Low-power mode 3.5 (10) | 2 V, 3 V |
1.3 | 1.5 | 2.2 | 1.9 | 2.8 | 5.0 | µA | ||
ILPM4.5 | Low-power mode 4.5 (11) | 2 V, 3 V |
0.3 | 0.32 | 0.66 | 0.38 | 0.57 | 2.55 | µA |
PARAMETER | PACKAGE | VALUE(1) | UNIT | |
---|---|---|---|---|
θJA | Junction-to-ambient thermal resistance, still air(2) | TSSOP-24 (PW) | 78.8 | °C/W |
θJC(TOP) | Junction-to-case (top) thermal resistance(3) | 19.4 | °C/W | |
θJB | Junction-to-board thermal resistance(5) | 36.7 | °C/W | |
ΨJB | Junction-to-board thermal characterization parameter | 36.2 | °C/W | |
ΨJT | Junction-to-top thermal characterization parameter | 0.5 | °C/W | |
θJC(BOTTOM) | Junction-to-case (bottom) thermal resistance(4) | N/A | °C/W | |
θJA | Junction-to-ambient thermal resistance, still air(2) | QFN-24 (RGE) | 42.1 | °C/W |
θJC(TOP) | Junction-to-case (top) thermal resistance(3) | 38.8 | °C/W | |
θJB | Junction-to-board thermal resistance(5) | 18.1 | °C/W | |
ΨJB | Junction-to-board thermal characterization parameter | 18.0 | °C/W | |
ΨJT | Junction-to-top thermal characterization parameter | 0.6 | °C/W | |
θJC(BOTTOM) | Junction-to-case (bottom) thermal resistance(4) | 2.8 | °C/W | |
θJA | Junction-to-ambient thermal resistance, still air(2) | SOIC-38 (DA) | 74.5 | °C/W |
θJC(TOP) | Junction-to-case (top) thermal resistance(3) | 22.0 | °C/W | |
θJB | Junction-to-board thermal resistance(5) | 40.7 | °C/W | |
ΨJB | Junction-to-board thermal characterization parameter | 40.3 | °C/W | |
ΨJT | Junction-to-top thermal characterization parameter | 0.9 | °C/W | |
θJC(BOTTOM) | Junction-to-case (bottom) thermal resistance(4) | N/A | °C/W | |
θJA | Junction-to-ambient thermal resistance, still air(2) | QFN-40 (RHA) | 37.8 | °C/W |
θJC(TOP) | Junction-to-case (top) thermal resistance(3) | 27.4 | °C/W | |
θJB | Junction-to-board thermal resistance(5) | 12.6 | °C/W | |
ΨJB | Junction-to-board thermal characterization parameter | 12.6 | °C/W | |
ΨJT | Junction-to-top thermal characterization parameter | 0.4 | °C/W | |
θJC(BOTTOM) | Junction-to-case (bottom) thermal resistance(4) | 3.6 | °C/W |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VIT+ | Positive-going input threshold voltage | 2 V | 0.80 | 1.40 | V | ||
3 V | 1.50 | 2.10 | |||||
VIT– | Negative-going input threshold voltage | 2 V | 0.45 | 1.10 | V | ||
3 V | 0.75 | 1.65 | |||||
Vhys | Input voltage hysteresis (VIT+ – VIT–) | 2 V | 0.25 | 0.8 | V | ||
3 V | 0.30 | 1.0 | |||||
RPull | Pullup or pulldown resistor | For pullup: VIN = VSS
For pulldown: VIN = VCC |
20 | 35 | 50 | kΩ | |
CI | Input capacitance | VIN = VSS or VCC | 5 | pF |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
t(int) | External interrupt timing (2) | External trigger pulse duration to set interrupt flag | 2 V, 3 V | 20 | ns |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
Ilkg(Px.x) | High-impedance leakage current | (1) (2) | 2 V, 3 V | –50 | 50 | nA |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
VOH | High-level output voltage | I(OHmax) = –1 mA (1) | 2 V | VCC – 0.25 | VCC | V |
I(OHmax) = –3 mA (2) | VCC – 0.60 | VCC | ||||
I(OHmax) = –2 mA (1) | 3 V | VCC – 0.25 | VCC | |||
I(OHmax) = –6 mA (2) | VCC – 0.60 | VCC | ||||
VOL | Low-level output voltage | I(OLmax) = 1 mA (1) | 2 V | VSS | VSS + 0.25 | V |
I(OLmax) = 3 mA (2) | VSS | VSS + 0.60 | ||||
I(OLmax) = 2 mA (1) | 3 V | VSS | VSS + 0.25 | |||
I(OLmax) = 6 mA (2) | VSS | VSS + 0.60 |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
fPx.y | Port output frequency (with load) | Px.y (1) (2) | 2 V | 16 | MHz | |
3 V | 24 | |||||
fPort_CLK | Clock output frequency | ACLK, SMCLK, or MCLK at configured output port, CL = 20 pF, no DC loading (2) |
2 V | 16 | MHz | |
3 V | 24 |
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC = 2.0 V | Measured at Px.y |
VCC = 3.0 V | Measured at Px.y |
VCC = 2.0 V | Measured at Px.y |
VCC = 3.0 V | Measured at Px.y |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
ΔIVCC.LF | Additional current consumption XT1 LF mode from lowest drive setting | fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {1}, CL,eff = 9 pF, TA = 25°C, |
3 V | 60 | nA | ||
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {2}, TA = 25°C, CL,eff = 9 pF |
3 V | 90 | |||||
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {3}, TA = 25°C, CL,eff = 12 pF |
3 V | 140 | |||||
fXT1,LF0 | XT1 oscillator crystal frequency, LF mode | XTS = 0, XT1BYPASS = 0 | 32768 | Hz | |||
fXT1,LF,SW | XT1 oscillator logic-level square-wave input frequency, LF mode | XTS = 0, XT1BYPASS = 1 (6) (7) | 10 | 32.768 | 50 | kHz | |
OALF | Oscillation allowance for LF crystals (8) | XTS = 0, XT1BYPASS = 0, XT1DRIVE = {0}, fXT1,LF = 32768 Hz, CL,eff = 6 pF |
210 | kΩ | |||
XTS = 0, XT1BYPASS = 0, XT1DRIVE = {3}, fXT1,LF = 32768 Hz, CL,eff = 12 pF |
300 | ||||||
Duty cycle, LF mode | XTS = 0, Measured at ACLK, fXT1,LF = 32768 Hz |
30% | 70% | ||||
fFault,LF | Oscillator fault frequency, LF mode (4) | XTS = 0 (3) | 10 | 10000 | Hz | ||
tSTART,LF | Start-up time, LF mode (9) | fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {0}, TA = 25°C, CL,eff = 6 pF |
3 V | 1000 | ms | ||
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {3}, TA = 25°C, CL,eff = 12 pF |
1000 | ||||||
CL,eff | Integrated effective load capacitance, LF mode (1) (2) | XTS = 0 | 1 | pF |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
IVCC,HF | XT1 oscillator crystal current HF mode | fOSC = 4 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {0}, TA = 25°C, CL,eff = 16 pF |
3 V | 175 | µA | ||
fOSC = 8 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {1}, TA = 25°C, CL,eff = 16 pF |
300 | ||||||
fOSC = 16 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {2}, TA = 25°C, CL,eff = 16 pF |
350 | ||||||
fOSC = 24 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {3}, TA = 25°C, CL,eff = 16 pF |
550 | ||||||
fXT1,HF0 | XT1 oscillator crystal frequency, HF mode 0 | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {0} (7) |
4 | 6 | MHz | ||
fXT1,HF1 | XT1 oscillator crystal frequency, HF mode 1 | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {1} (7) |
6 | 10 | MHz | ||
fXT1,HF2 | XT1 oscillator crystal frequency, HF mode 2 | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {2} (7) |
10 | 16 | MHz | ||
fXT1,HF3 | XT1 oscillator crystal frequency, HF mode 3 | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {3} (7) |
16 | 24 | MHz | ||
fXT1,HF,SW | XT1 oscillator logic-level square-wave input frequency, HF mode | XTS = 1, XT1BYPASS = 1 (6) (7) |
1 | 24 | MHz | ||
OAHF | Oscillation allowance for HF crystals (8) | XTS = 1, XT1BYPASS = 0, XT1DRIVE = {0}, fXT1,HF = 4 MHz, CL,eff = 16 pF |
450 | Ω | |||
XTS = 1, XT1BYPASS = 0, XT1DRIVE = {1}, fXT1,HF = 8 MHz, CL,eff = 16 pF |
320 | ||||||
XTS = 1, XT1BYPASS = 0, XT1DRIVE = {2}, fXT1,HF = 16 MHz, CL,eff = 16 pF |
200 | ||||||
XTS = 1, XT1BYPASS = 0, XT1DRIVE = {3}, fXT1,HF = 24 MHz, CL,eff = 16 pF |
200 | ||||||
tSTART,HF | Start-up time, HF mode (9) | fOSC = 4 MHz, XTS = 1, XT1BYPASS = 0, XT1DRIVE = {0}, TA = 25°C, CL,eff = 16 pF |
3 V | 8 | ms | ||
fOSC = 24 MHz, XTS = 1, XT1BYPASS = 0, XT1DRIVE = {3}, TA = 25°C, CL,eff = 16 pF |
2 | ||||||
CL,eff | Integrated effective load capacitance (1) (2) | XTS = 1 | 1 | pF | |||
Duty cycle, HF mode | XTS = 1, Measured at ACLK, fXT1,HF2 = 24 MHz |
40% | 50% | 60% | |||
fFault,HF | Oscillator fault frequency, HF mode (4) | XTS = 1 (3) | 145 | 900 | kHz |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fVLO | VLO frequency | Measured at ACLK | 2 V to 3.6 V | 5 | 8.3 | 13 | kHz |
dfVLO/dT | VLO frequency temperature drift | Measured at ACLK (1) | 2 V to 3.6 V | 0.5 | %/°C | ||
dfVLO/dVCC | VLO frequency supply voltage drift | Measured at ACLK (2) | 2 V to 3.6 V | 4 | %/V | ||
fVLO,DC | Duty cycle | Measured at ACLK | 2 V to 3.6 V | 40% | 50% | 60% |
NOTE
In LPM3, the VLO frequency varies by up to ±6% (typical), due to bias current sampling. This frequency variation is not a violation VLO specifications (see Section 5.15).
PARAMETER | TEST CONDITIONS | VCC
TA |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fDCO,LO | DCO frequency low, trimmed | Measured at ACLK, DCORSEL = 0 |
2 V to 3.6 V –40°C to 85°C |
5.37 | ±3.5% | MHz | |
2 V to 3.6 V 0°C to 50°C |
5.37 | ±2.0% | |||||
fDCO,MID | DCO frequency mid, trimmed | Measured at ACLK, DCORSEL = 0 |
2 V to 3.6 V –40°C to 85°C |
6.67 | ±3.5% | MHz | |
2 V to 3.6 V 0°C to 50°C |
6.67 | ±2.0% | |||||
fDCO,HI | DCO frequency high, trimmed | Measured at ACLK, DCORSEL = 0 |
2 V to 3.6 V –40°C to 85°C |
8 | ±3.5% | MHz | |
2 V to 3.6 V 0°C to 50°C |
8 | ±2.0% | |||||
fDCO,DC | Duty cycle | Measured at ACLK, divide by 1, No external divide, all DCO settings |
2 V to 3.6 V –40°C to 85°C |
40% | 50% | 60% |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
IMODOSC | Current consumption | Enabled | 2 V to 3.6 V | 44 | 80 | µA | |
fMODOSC | MODOSC frequency | 2 V to 3.6 V | 4.5 | 5.0 | 5.5 | MHz | |
fMODOSC,DC | Duty cycle | Measured at ACLK, divide by 1 | 2 V to 3.6 V | 40% | 50% | 60% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VCORE(AM) | Core voltage, active mode | 2 V ≤ DVCC ≤ 3.6 V | 1.5 | V | ||
VCORE(LPM) | Core voltage, low-current mode | 2 V ≤ DVCC ≤ 3.6 V | 1.5 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ISVSH,AM | SVSH current consumption, active mode | VCC = 3.6 V | 5 | µA | ||
ISVSH,LPM | SVSH current consumption, low power modes | VCC = 3.6 V | 0.8 | 1.5 | µA | |
VSVSH- | SVSH on voltage level, falling supply voltage | 1.83 | 1.88 | 1.93 | V | |
VSVSH+ | SVSH off voltage level, rising supply voltage | 1.88 | 1.93 | 1.98 | V | |
tPD,SVSH, AM | SVSH propagation delay, active mode | dVCC/dt = 10 mV/µs | 10 | µs | ||
tPD,SVSH, LPM | SVSH propagation delay, low power modes | dVCC/dt = 1 mV/µs | 30 | µs | ||
ISVSL | SVSL current consumption | 0.3 | 0.5 | µA | ||
VSVSL– | SVSL on voltage level | 1.42 | V | |||
VSVSL+ | SVSL off voltage level | 1.47 | V |
PARAMETER | TEST CONDITIONS | VCC
TA |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tWAKE-UP LPM0 | Wake-up time from LPM0 to active mode (1) | 2 V, 3 V –40°C to 85°C |
0.58 | 1 | µs | ||
tWAKE-UP LPM12 | Wake-up time from LPM1, LPM2 to active mode (1) | 2 V, 3 V –40°C to 85°C |
12 | 25 | µs | ||
tWAKE-UP LPM34 | Wake-up time from LPM3 or LPM4 to active mode (1) | 2 V, 3 V –40°C to 85°C |
78 | 120 | µs | ||
tWAKE-UP LPMx.5 | Wake-up time from LPM3.5 or LPM4.5 to active mode (1) | 2 V, 3 V 0°C to 85°C |
310 | 575 | µs | ||
2 V, 3 V –40°C to 85°C |
310 | 1100 | |||||
tWAKE-UP RESET | Wake-up time from RST to active mode (2) | VCC stable |
2 V, 3 V –40°C to 85°C |
230 | 280 | µs | |
tWAKE-UP BOR | Wake-up time from BOR or power-up to active mode | dVCC/dt = 2400 V/s | 2 V, 3 V –40°C to 85°C |
1.6 | ms | ||
tRESET | Pulse duration required at RST/NMI terminal to accept a reset event(3) | 2 V, 3 V –40°C to 85°C |
4 | ns |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fTA | Timer_A input clock frequency | Internal: SMCLK, ACLK External: TACLK Duty cycle = 50% ±10% |
2 V, 3 V | 8 | MHz | ||
tTA,cap | Timer_A capture timing | All capture inputs, Minimum pulse duration required for capture | 2 V, 3 V | 20 | ns |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fTB | Timer_B input clock frequency | Internal: SMCLK, ACLK External: TBCLK Duty cycle = 50% ±10% |
2 V, 3 V | 8 | MHz | ||
tTB,cap | Timer_B capture timing | All capture inputs, Minimum pulse duration required for capture | 2 V, 3 V | 20 | ns |
PARAMETER | CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ±10% |
fSYSTEM | MHz | |||
fBITCLK | BITCLK clock frequency (equals baud rate in MBaud) |
5 | MHz |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tt | UART receive deglitch time(1) | UCGLITx = 0 | 2 V, 3 V | 5 | 15 | 20 | ns |
UCGLITx = 1 | 20 | 45 | 60 | ||||
UCGLITx = 2 | 35 | 80 | 120 | ||||
UCGLITx = 3 | 50 | 110 | 180 |
PARAMETER | CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK, ACLK Duty cycle = 50% ±10% |
fSYSTEM | MHz |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tSTE,LEAD | STE lead time, STE active to clock | UCSTEM = 0, UCMODEx = 01 or 10 |
2 V, 3 V | 1 | UCxCLK cycles | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
2 V, 3 V | 1 | |||||
tSTE,LAG | STE lag time, Last clock to STE inactive | UCSTEM = 0, UCMODEx = 01 or 10 |
2 V, 3 V | 1 | UCxCLK cycles | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
2 V, 3 V | 1 | |||||
tSTE,ACC | STE access time, STE active to SIMO data out | UCSTEM = 0, UCMODEx = 01 or 10 |
2 V, 3 V | 55 | ns | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
2 V, 3 V | 35 | |||||
tSTE,DIS | STE disable time, STE inactive to SIMO high impedance | UCSTEM = 0, UCMODEx = 01 or 10 |
2 V, 3 V | 40 | ns | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
2 V, 3 V | 30 | |||||
tSU,MI | SOMI input data setup time | 2 V | 35 | ns | |||
3 V | 35 | ||||||
tHD,MI | SOMI input data hold time | 2 V | 0 | ns | |||
3 V | 0 | ||||||
tVALID,MO | SIMO output data valid time (2) | UCLK edge to SIMO valid, CL = 20 pF |
2 V | 30 | ns | ||
3 V | 30 | ||||||
tHD,MO | SIMO output data hold time (3) | CL = 20 pF | 2 V | 0 | ns | ||
3 V | 0 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tSTE,LEAD | STE lead time, STE active to clock | 2 V | 7 | ns | |||
3 V | 7 | ||||||
tSTE,LAG | STE lag time, Last clock to STE inactive | 2 V | 0 | ns | |||
3 V | 0 | ||||||
tSTE,ACC | STE access time, STE active to SOMI data out | 2 V | 65 | ns | |||
3 V | 40 | ||||||
tSTE,DIS | STE disable time, STE inactive to SOMI high impedance | 2 V | 40 | ns | |||
3 V | 35 | ||||||
tSU,SI | SIMO input data setup time | 2 V | 2 | ns | |||
3 V | 2 | ||||||
tHD,SI | SIMO input data hold time | 2 V | 5 | ns | |||
3 V | 5 | ||||||
tVALID,SO | SOMI output data valid time (2) | UCLK edge to SOMI valid, CL = 20 pF |
2 V | 30 | ns | ||
3 V | 30 | ||||||
tHD,SO | SOMI output data hold time (3) | CL = 20 pF | 2 V | 4 | ns | ||
3 V | 4 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ±10% |
fSYSTEM | MHz | |||
fSCL | SCL clock frequency | 2 V, 3 V | 0 | 400 | kHz | ||
tHD,STA | Hold time (repeated) START | fSCL = 100 kHz | 2 V, 3 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSU,STA | Setup time for a repeated START | fSCL = 100 kHz | 2 V, 3 V | 4.7 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tHD,DAT | Data hold time | 2 V, 3 V | 0 | ns | |||
tSU,DAT | Data setup time | 2 V, 3 V | 250 | ns | |||
tSU,STO | Setup time for STOP | fSCL = 100 kHz | 2 V, 3 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSP | Pulse duration of spikes suppressed by input filter | UCGLITx = 0 | 2 V, 3 V | 50 | 600 | ns | |
UCGLITx = 1 | 25 | 300 | |||||
UCGLITx = 2 | 12.5 | 150 | |||||
UCGLITx = 3 | 6.25 | 75 | |||||
tTIMEOUT | Clock low time-out | UCCLTOx = 1 | 2 V, 3 V | 27 | ms | ||
UCCLTOx = 2 | 30 | ||||||
UCCLTOx = 3 | 33 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
AVCC | Analog supply voltage | AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V |
2.0 | 3.6 | V | ||
V(Ax) | Analog input voltage range | All ADC10 pins | 0 | AVCC | V | ||
IADC10_A | Operating supply current into AVCC terminal, reference current not included | fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0 |
2 V | 90 | 140 | µA | |
3 V | 100 | 160 | |||||
CI | Input capacitance | Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad | 2.2 V | 6 | 8 | pF | |
RI | Input MUX ON resistance | AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC | 36 | kΩ |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fADC10CLK | For specified performance of ADC10 linearity parameters | 2 V to 3.6 V | 0.45 | 5 | 5.5 | MHz | |
fADC10OSC | Internal ADC10 oscillator (MODOSC) | ADC10DIV = 0, fADC10CLK = fADC10OSC | 2 V to 3.6 V | 4.5 | 4.5 | 5.5 | MHz |
tCONVERT | Conversion time | REFON = 0, Internal oscillator, 12 ADC10CLK cycles, 10-bit mode, fADC10OSC = 4.5 MHz to 5.5 MHz |
2 V to 3.6 V | 2.18 | 2.67 | µs | |
External fADC10CLK from ACLK, MCLK, or SMCLK, ADC10SSEL ≠ 0 | 2 V to 3.6 V | (1) | |||||
tADC10ON | Turnon settling time of the ADC | The error in a conversion started after tADC10ON is less than ±0.5 LSB, Reference and input signal already settled |
100 | ns | |||
tSample | Sampling time | RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF, Approximately eight Tau (τ) are required to get an error of less than ±0.5 LSB |
2 V | 1.5 | µs | ||
3 V | 2.0 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
EI | Integral linearity error | 1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V | 2 V to 3.6 V | –1.4 | 1.4 | LSB | |
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC | –1.1 | 1.1 | |||||
ED | Differential linearity error | (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) | 2 V to 3.6 V | –1 | 1 | LSB | |
EO | Offset error | (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) | 2 V to 3.6 V | –6.5 | 6.5 | mV | |
EG | Gain error, external reference | (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) | 2 V to 3.6 V | –1.2 | 1.2 | LSB | |
Gain error, internal reference (1) | –4% | 4% | |||||
ET | Total unadjusted error, external reference | (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–) | 2 V to 3.6 V | –2 | 2 | LSB | |
Total unadjusted error, internal reference (1) | –4% | 4% |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VeREF+ | Positive external reference voltage input | VeREF+ > VeREF– (2) | 1.4 | AVCC | V | ||
VeREF– | Negative external reference voltage input | VeREF+ > VeREF– (3) | 0 | 1.2 | V | ||
(VeREF+ – VREF–/VeREF–) |
Differential external reference voltage input | VeREF+ > VeREF– (4) | 1.4 | AVCC | V | ||
IVeREF+, IVeREF– |
Static input current | 1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 1h, Conversion rate 200 ksps |
2.2 V, 3 V | –6 | 6 | µA | |
1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 8h, Conversion rate 20 ksps |
2.2 V, 3 V | –1 | 1 | ||||
CVREF+, CVREF- |
Capacitance at VREF+ or VREF- terminal(5) | 10 | µF |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VREF+ | Positive built-in reference voltage output | REFVSEL = {2} for 2.5 V, REFON = 1 | 3 V | 2.4 | 2.5 | 2.6 | V |
REFVSEL = {1} for 2 V, REFON = 1 | 3 V | 1.92 | 2.0 | 2.08 | |||
REFVSEL = {0} for 1.5 V, REFON = 1 | 3 V | 1.44 | 1.5 | 1.56 | |||
AVCC(min) | AVCC minimum voltage, Positive built-in reference active | REFVSEL = {0} for 1.5 V | 2.0 | V | |||
REFVSEL = {1} for 2 V | 2.2 | ||||||
REFVSEL = {2} for 2.5 V | 2.7 | ||||||
IREF+ | Operating supply current into AVCC terminal (1) | fADC10CLK = 5 MHz, REFON = 1, REFBURST = 0 |
3 V | 33 | 45 | µA | |
TREF+ | Temperature coefficient of built-in reference | REFVSEL = (0, 1, 2}, REFON = 1 | ±35 | ppm/ °C | |||
PSRR_DC | Power supply rejection ratio (DC) | AVCC = AVCC (min) - AVCC(max), TA = 25°C, REFON = 1, REFVSEL = (0} for 1.5 V |
1600 | µV/V | |||
AVCC = AVCC (min) - AVCC(max), TA = 25°C, REFON = 1, REFVSEL = (1} for 2 V |
1900 | ||||||
AVCC = AVCC (min) - AVCC(max), TA = 25°C, REFON = 1, REFVSEL = (2} for 2.5 V |
3600 | ||||||
tSETTLE | Settling time of reference voltage (2) | AVCC = AVCC (min) - AVCC(max), REFVSEL = (0, 1, 2}, REFON = 0 → 1 |
30 | µs |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VSENSOR | See (1) | ADC10ON = 1, INCH = 0Ah, TA = 0°C |
2 V, 3 V | 790 | mV | ||
TCSENSOR | ADC10ON = 1, INCH = 0Ah | 2 V, 3 V | 2.55 | mV/°C | |||
tSENSOR(sample) | Sample time required if channel 10 is selected (2) | ADC10ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB |
2 V | 30 | µs | ||
3 V | 30 | ||||||
VMID | AVCC divider at channel 11 | ADC10ON = 1, INCH = 0Bh, VMID is ~0.5 × VAVCC |
2 V | 0.97 | 1.0 | 1.03 | V |
3 V | 1.46 | 1.5 | 1.54 | ||||
tVMID(sample) | Sample time required if channel 11 is selected (3) | ADC10ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB |
2 V, 3 V | 1000 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tpd | Propagation delay, AVCC = 2 V to 3.6 V |
Overdrive = 10 mV, VIN- = (VIN+ – 400 mV) to (VIN+ + 10 mV) |
50 | 100 | 200 | ns |
Overdrive = 100 mV, VIN- = (VIN+ – 400 mV) to (VIN+ + 100 mV) |
80 | |||||
Overdrive = 250 mV, (VIN+ – 400 mV) to (VIN+ + 250 mV) |
50 | |||||
tfilter | Filter timer added to the propagation delay of the comparator | CDF = 1, CDFDLY = 00 | 0.3 | 0.5 | 0.9 | µs |
CDF = 1, CDFDLY = 01 | 0.5 | 0.9 | 1.5 | |||
CDF = 1, CDFDLY = 10 | 0.9 | 1.6 | 2.8 | |||
CDF = 1, CDFDLY = 11 | 1.6 | 3.0 | 5.5 | |||
Voffset | Input offset | AVCC = 2 V to 3.6 V | –20 | 20 | mV | |
Vic | Common mode input range | AVCC = 2 V to 3.6 V | 0 | AVCC - 1 | V | |
Icomp(AVCC) | Comparator only | CDON = 1, AVCC = 2 V to 3.6 V | 29 | 34 | µA | |
Iref(AVCC) | Reference buffer and R‑ladder | CDREFLx = 01, AVCC = 2 V to 3.6 V | 20 | 24 | µA | |
tenable,comp | Comparator enable time | CDON = 0 to CDON = 1, AVCC = 2 V to 3.6 V |
1.1 | 2.0 | µs | |
tenable,rladder | Resistor ladder enable time | CDON = 0 to CDON = 1, AVCC = 2 V to 3.6 V |
1.1 | 2.0 | µs | |
VCB_REF | Reference voltage for a tap | VIN = voltage input to the R-ladder, n = 0 to 31 |
VIN × (n + 0.5) / 32 | VIN × (n + 1) / 32 |
VIN × (n + 1.5) / 32 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DVCC(WRITE) | Write supply voltage | 2.0 | 3.6 | V | ||
tWRITE | Word or byte write time | 120 | ns | |||
tACCESS | Read access time (1) | 60 | ns | |||
tPRECHARGE | Precharge time (1) | 60 | ns | |||
tCYCLE | Cycle time, read or write operation (1) | 120 | ns | |||
Read and write endurance | 1015 | cycles | ||||
tRetention | Data retention duration | TJ = 25°C | 100 | years | ||
TJ = 70°C | 40 | |||||
TJ = 85°C | 10 |
PARAMETER | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSBW | Spy-Bi-Wire input frequency | 2 V, 3 V | 0 | 20 | MHz | |
tSBW,Low | Spy-Bi-Wire low clock pulse duration | 2 V, 3 V | 0.025 | 15 | µs | |
tSBW, En | Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) | 2 V, 3 V | 1 | µs | ||
tSBW,Rst | Spy-Bi-Wire return to normal operation time | 19 | 35 | µs | ||
fTCK | TCK input frequency, 4-wire JTAG (2) | 2 V | 0 | 5 | MHz | |
3 V | 0 | 10 | ||||
Rinternal | Internal pulldown resistance on TEST | 2 V, 3 V | 20 | 35 | 50 | kΩ |
Figure 6-1 shows the functional block diagram for the MSP430FR5721, MSP430FR5725, and MSP430FR5729 in the RHA package.
Figure 6-2 shows the functional block diagram for the MSP430FR5723 and MSP430FR5727 devices in the RHA package.
Figure 6-3 shows the functional block diagram for the MSP430FR5721, MSP430FR5725, and MSP430FR5729 devices in the DA package.
Figure 6-4 shows the functional block diagram for the MSP430FR5723 and MSP430FR5727 devices in the DA package.
Figure 6-5 shows the functional block diagram for the MSP430FR5720, MSP430FR5724, and MSP430FR5728 devices in the RGE package.
Figure 6-6 shows the functional block diagram for the MSP430FR5722 and MSP430FR5726 devices in the RGE package.
Figure 6-7 shows the functional block diagram for the MSP430FR5720, MSP430FR5724, and MSP430FR5728 devices in the PW package.
Figure 6-8 shows the functional block diagram for the MSP430FR5722 and MSP430FR5726 devices in the PW package.
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.
The MSP430 has one active mode and seven software-selectable low-power modes of operation. An interrupt event can wake up the device from low-power modes LPM0 through LPM4, service the request, and restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
The following eight operating modes can be configured by software:
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE | INTERRUPT FLAG | SYSTEM INTERRUPT | WORD ADDRESS | PRIORITY |
---|---|---|---|---|
System Reset
Power-Up, Brownout, Supply Supervisors External Reset RST Watchdog Time-out (Watchdog mode) WDT, FRCTL MPU, CS, PMM Password Violation FRAM double bit error detection MPU segment violation Software POR, BOR |
SVSLIFG, SVSHIFG PMMRSTIFG WDTIFG WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW DBDIFG MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG PMMPORIFG, PMMBORIFG (SYSRSTIV) (1) (3) |
Reset | 0FFFEh | 63, highest |
System NMI
Vacant Memory Access JTAG Mailbox FRAM access time error FRAM single, double bit error detection |
VMAIFG JMBNIFG, JMBOUTIFG ACCTIMIFG SBDIFG, DBDIFG (SYSSNIV) (1) |
(Non)maskable | 0FFFCh | 62 |
User NMI
External NMI Oscillator Fault |
NMIIFG, OFIFG (SYSUNIV) (1) (3) |
(Non)maskable | 0FFFAh | 61 |
Comparator_D | Comparator_D interrupt flags (CBIV) (1) (2) |
Maskable | 0FFF8h | 60 |
TB0 | TB0CCR0 CCIFG0 (2) | Maskable | 0FFF6h | 59 |
TB0 | TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2, TB0IFG (TB0IV) (1) (2) |
Maskable | 0FFF4h | 58 |
Watchdog Timer (Interval Timer Mode) |
WDTIFG | Maskable | 0FFF2h | 57 |
eUSCI_A0 Receive and Transmit | UCA0RXIFG, UCA0TXIFG (SPI mode) UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG, UXA0TXIFG (UART mode) (UCA0IV) (1) (2) |
Maskable | 0FFF0h | 56 |
eUSCI_B0 Receive and Transmit | UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG, UCB0TXIFG (SPI mode) UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG, UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0, UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2, UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3, UCB0CNTIFG, UCB0BIT9IFG (I2C mode) (UCB0IV) (1) (2) |
Maskable | 0FFEEh | 55 |
ADC10_B | ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG, ADC10LOIFG ADC10INIFG, ADC10IFG0 (ADC10IV) (1) (2) (5) |
Maskable | 0FFECh | 54 |
TA0 | TA0CCR0 CCIFG0 (2) | Maskable | 0FFEAh | 53 |
TA0 | TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2, TA0IFG (TA0IV) (1) (2) |
Maskable | 0FFE8h | 52 |
eUSCI_A1 Receive and Transmit | UCA1RXIFG, UCA1TXIFG (SPI mode) UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG, UXA1TXIFG (UART mode) (UCA1IV) (1) (2) |
Maskable | 0FFE6h | 51 |
DMA | DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (2) |
Maskable | 0FFE4h | 50 |
TA1 | TA1CCR0 CCIFG0 (2) | Maskable | 0FFE2h | 49 |
TA1 | TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV) (1) (2) |
Maskable | 0FFE0h | 48 |
I/O Port P1 | P1IFG.0 to P1IFG.7 (P1IV) (1) (2) |
Maskable | 0FFDEh | 47 |
TB1 | TB1CCR0 CCIFG0 (2) | Maskable | 0FFDCh | 46 |
TB1 | TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2, TB1IFG (TB1IV) (1) (2) |
Maskable | 0FFDAh | 45 |
I/O Port P2 | P2IFG.0 to P2IFG.7 (P2IV) (1) (2) |
Maskable | 0FFD8h | 44 |
TB2 | TB2CCR0 CCIFG0 (2) | Maskable | 0FFD6h | 43 |
TB2 | TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2, TB2IFG (TB2IV) (1) (2) |
Maskable | 0FFD4h | 42 |
I/O Port P3 | P3IFG.0 to P3IFG.7 (P3IV) (1) (2) |
Maskable | 0FFD2h | 41 |
I/O Port P4 | P4IFG.0 to P4IFG.2 (P4IV) (1) (2) |
Maskable | 0FFD0h | 40 |
RTC_B | RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV) (1) (2) |
Maskable | 0FFCEh | 39 |
Reserved | Reserved (4) | 0FFCCh | 38 | |
⋮ | ⋮ | |||
0FF80h | 0, lowest |
Table 6-2 describes the memory organization for all device variants.
MSP430FR5726 MSP430FR5727 MSP430FR5728 MSP430FR5729 |
MSP430FR5722 MSP430FR5723 MSP430FR5724 MSP430FR5725 |
MSP430FR5720 MSP430FR5721 |
||
---|---|---|---|---|
Memory (FRAM) Main: interrupt vectors Main: code memory |
Total Size | 15.5KB 00FFFFh–00FF80h 00FF7Fh–00C200h |
8.0KB 00FFFFh–00FF80h 00FF7Fh–00E000h |
4KB 00FFFFh–00FF80h 00FF7Fh–00F000h |
RAM | 1KB 001FFFh–001C00h |
1KB 001FFFh–001C00h |
1KB 001FFFh–001C00h |
|
Device Descriptor Info (TLV) (FRAM) | 128 B 001A7Fh–001A00h |
128 B 001A7Fh–001A00h |
128 B 001A7Fh–001A00h |
|
Information memory (FRAM) | N/A | 0019FFh–001980h Address space mirrored to Info A |
0019FFh–001980h Address space mirrored to Info A |
0019FFh–001980h Address space mirrored to Info A |
N/A | 00197Fh–001900h Address space mirrored to Info B |
00197Fh–001900h Address space mirrored to Info B |
00197Fh–001900h Address space mirrored to Info B |
|
Info A | 128 B 0018FFh–001880h |
128 B 0018FFh–001880h |
128 B 0018FFh–001880h |
|
Info B | 128 B 00187Fh–001800h |
128 B 00187Fh–001800h |
128 B 00187Fh–001800h |
|
Bootloader (BSL) memory (ROM) | BSL 3 | 512 B 0017FFh–001600h |
512 B 0017FFh–001600h |
512 B 0017FFh–001600h |
BSL 2 | 512 B 0015FFh–001400h |
512 B 0015FFh–001400h |
512 B 0015FFh–001400h |
|
BSL 1 | 512 B 0013FFh–001200h |
512 B 0013FFh–001200h |
512 B 0013FFh–001200h |
|
BSL 0 | 512 B 0011FFh–001000h |
512 B 0011FFh–001000h |
512 B 0011FFh–001000h |
|
Peripherals | Size | 4KB 000FFFh–0h |
4KB 000FFFh–0h |
4KB 000FFFh–0h |
The BSL enables users to program the FRAM or RAM using a UART serial interface. Access to the device memory by the BSL is protected by an user-defined password. Use of the BSL requires four pins (see Table 6-3). BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the BSL and its implementation, see the MSP430 Programming With the Bootloader User's Guide.
DEVICE SIGNAL | BSL FUNCTION |
---|---|
RST/NMI/SBWTDIO | Entry sequence signal |
TEST/SBWTCK | Entry sequence signal |
P2.0 | Data transmit |
P2.1 | Data receive |
VCC | Power supply |
VSS | Ground supply |
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. Table 6-4 lists the JTAG pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface.
DEVICE SIGNAL | DIRECTION | FUNCTION |
---|---|---|
PJ.3/TCK | IN | JTAG clock input |
PJ.2/TMS | IN | JTAG state control |
PJ.1/TDI/TCLK | IN | JTAG data input, TCLK input |
PJ.0/TDO | OUT | JTAG data output |
TEST/SBWTCK | IN | Enable JTAG pins |
RST/NMI/SBWTDIO | IN | External reset |
VCC | Power supply | |
VSS | Ground supply |
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-5 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface.
DEVICE SIGNAL | DIRECTION | FUNCTION |
---|---|---|
TEST/SBWTCK | IN | Spy-Bi-Wire clock input |
RST/NMI/SBWTDIO | IN, OUT | Spy-Bi-Wire data input and output |
VCC | Power supply | |
VSS | Ground supply |
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. Features of the FRAM include:
For important software design information regarding FRAM including but not limited to partitioning the memory layout according to application-specific code, constant, and data space requirements, the use of FRAM to optimize application energy consumption, and the use of the memory protection unit (MPU) to maximize application robustness by protecting the program code against unintended write accesses, see MSP430™ FRAM Technology – How To and Best Practices.
The FRAM can be protected from inadvertent CPU execution or write access by the MPU. Features of the MPU include:
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be managed using all instructions. For complete module descriptions, see the MSP430FR57xx Family User's Guide.
Up to four 8-bit I/O ports are implemented:
The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF mode), an internal very-low-power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator XT1 (HF mode). The clock system module is designed to meet the requirements of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The clock system module provides the following clock signals:
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the primary and core supplies.
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations.
The RTC_B module contains an integrated real-time clock (RTC) (calendar mode). Calendar mode integrates an internal calendar which compensates for months with fewer than 31 days and includes leap year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. RTC operation is available in LPM3.5 mode to minimize power consumption.
The primary function of the WDT_A module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
The SYS module handles many of the system functions within the device. These include power-on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators (see Table 6-6), bootloader entry mechanisms, and configuration management (device descriptors). It also includes a data exchange mechanism using JTAG called a JTAG mailbox that can be used in the application.
The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_B conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 6-7 lists all triggers to start DMA transfers.
TRIGGER | CHANNEL 0 | CHANNEL 1 | CHANNEL 2 |
---|---|---|---|
0 | DMAREQ | DMAREQ | DMAREQ |
1 | TA0CCR0 CCIFG | TA0CCR0 CCIFG | TA0CCR0 CCIFG |
2 | TA0CCR2 CCIFG | TA0CCR2 CCIFG | TA0CCR2 CCIFG |
3 | TA1CCR0 CCIFG | TA1CCR0 CCIFG | TA1CCR0 CCIFG |
4 | TA1CCR2 CCIFG | TA1CCR2 CCIFG | TA1CCR2 CCIFG |
5 | Reserved | Reserved | Reserved |
6 | Reserved | Reserved | Reserved |
7 | TB0CCR0 CCIFG | TB0CCR0 CCIFG | TB0CCR0 CCIFG |
8 | TB0CCR2 CCIFG | TB0CCR2 CCIFG | TB0CCR2 CCIFG |
9 | TB1CCR0 CCIFG (3) | TB1CCR0 CCIFG (3) | TB1CCR0 CCIFG (3) |
10 | TB1CCR2 CCIFG (3) | TB1CCR2 CCIFG (3) | TB1CCR2 CCIFG (3) |
11 | TB2CCR0 CCIFG (4) | TB2CCR0 CCIFG (4) | TB2CCR0 CCIFG (4) |
12 | TB2CCR2 CCIFG (4) | TB2CCR2 CCIFG (4) | TB2CCR2 CCIFG (4) |
13 | Reserved | Reserved | Reserved |
14 | UCA0RXIFG | UCA0RXIFG | UCA0RXIFG |
15 | UCA0TXIFG | UCA0TXIFG | UCA0TXIFG |
16 | UCA1RXIFG (5) | UCA1RXIFG (5) | UCA1RXIFG (5) |
17 | UCA1TXIFG (5) | UCA1TXIFG (5) | UCA1TXIFG (5) |
18 | UCB0RXIFG0 | UCB0RXIFG0 | UCB0RXIFG0 |
19 | UCB0TXIFG0 | UCB0TXIFG0 | UCB0TXIFG0 |
20 | UCB0RXIFG1 | UCB0RXIFG1 | UCB0RXIFG1 |
21 | UCB0TXIFG1 | UCB0TXIFG1 | UCB0TXIFG1 |
22 | UCB0RXIFG2 | UCB0RXIFG2 | UCB0RXIFG2 |
23 | UCB0TXIFG2 | UCB0TXIFG2 | UCB0TXIFG2 |
24 | UCB0RXIFG3 | UCB0RXIFG3 | UCB0RXIFG3 |
25 | UCB0TXIFG3 | UCB0TXIFG3 | UCB0TXIFG3 |
26 | ADC10IFGx (2) | ADC10IFGx (2) | ADC10IFGx (2) |
27 | Reserved | Reserved | Reserved |
28 | Reserved | Reserved | Reserved |
29 | MPY ready | MPY ready | MPY ready |
30 | DMA2IFG | DMA0IFG | DMA1IFG |
31 | DMAE0 | DMAE0 | DMAE0 |
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each eUSCI module contains two portions, A and B.
The eUSCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module provides support for SPI (3-pin or 4-pin) or I2C.
The MSP430FR572x series include one or two eUSCI_An modules (eUSCI_A0, eUSCI_A1) and one eUSCI_Bn module (eUSCI_B).
TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. TA0 and TA1 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-8 and Table 6-9). TA0 and TA1 have extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
RHA | RGE | DA | PW | RHA | RGE | DA | PW | |||||
3-P1.2 | 3-P1.2 | 7-P1.2 | 7-P1.2 | TA0CLK | TACLK | Timer | N/A | N/A | ||||
ACLK (internal) | ACLK | |||||||||||
SMCLK (internal) | SMCLK | |||||||||||
3-P1.2 | 3-P1.2 | 7-P1.2 | 7-P1.2 | TA0CLK | TACLK | |||||||
28-P1.6 | 16-P1.6 | 30-P1.6 | 22-P1.6 | TA0.0 | CCI0A | CCR0 | TA0 | TA0.0 | 28-P1.6 | 16-P1.6 | 30-P1.6 | 22-P1.6 |
34-P2.3 | N/A | 36-P2.3 | 27-P2.3 | TA0.0 | CCI0B | 34-P2.3 | N/A | 36-P2.3 | 27-P2.3 | |||
DVSS | GND | |||||||||||
DVCC | VCC | |||||||||||
1-P1.0 | 1-P1.0 | 5-P1.0 | 5-P1.0 | TA0.1 | CCI1A | CCR1 | TA1 | TA0.1 | 1-P1.0 | 1-P1.0 | 5-P1.0 | 5-P1.0 |
CDOUT (internal) | CCI1B | ADC10 (internal) (1)
ADC10SHSx = {1} |
ADC10 (internal) (1)
ADC10SHSx = {1} |
ADC10 (internal) (1)
ADC10SHSx = {1} |
ADC10 (internal) (1)
ADC10SHSx = {1} |
|||||||
DVSS | GND | |||||||||||
DVCC | VCC | |||||||||||
2-P1.1 | 2-P1.1 | 6-P1.1 | 6-P1.1 | TA0.2 | CCI2A | CCR2 | TA2 | TA0.2 | 2-P1.1 | 2-P1.1 | 6-P1.1 | 6-P1.1 |
ACLK (internal) | CCI2B | |||||||||||
DVSS | GND | |||||||||||
DVCC | VCC |
INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
RHA | RGE | DA | PW | RHA | RGE | DA | PW | |||||
2-P1.1 | 2-P1.1 | 6-P1.1 | 6-P1.1 | TA1CLK | TACLK | Timer | N/A | N/A | ||||
ACLK (internal) | ACLK | |||||||||||
SMCLK (internal) | SMCLK | |||||||||||
2-P1.1 | 2-P1.1 | 6-P1.1 | 6-P1.1 | TA1CLK | TACLK | |||||||
29-P1.7 | 17-P1.7 | 31-P1.7 | 23-P1.7 | TA1.0 | CCI0A | CCR0 | TA0 | TA1.0 | 29-P1.7 | 17-P1.7 | 31-P1.7 | 23-P1.7 |
35-P2.4 | N/A | 37-P2.4 | 28-P2.4 | TA1.0 | CCI0B | 35-P2.4 | N/A | 37-P2.4 | 28-P2.4 | |||
DVSS | GND | |||||||||||
DVCC | VCC | |||||||||||
3-P1.2 | 3-P1.2 | 7-P1.2 | 7-P1.2 | TA1.1 | CCI1A | CCR1 | TA1 | TA1.1 | 3-P1.2 | 3-P1.2 | 7-P1.2 | 7-P1.2 |
CDOUT (internal) | CCI1B | |||||||||||
DVSS | GND | |||||||||||
DVCC | VCC | |||||||||||
8-P1.3 | 4-P1.3 | 12-P1.3 | 8-P1.3 | TA1.2 | CCI2A | CCR2 | TA2 | TA1.2 | 8-P1.3 | 4-P1.3 | 12-P1.3 | 8-P1.3 |
ACLK (internal) | CCI2B | |||||||||||
DVSS | GND | |||||||||||
DVCC | VCC |
TB0, TB1, and TB2 are 16-bit timers/counters (Timer_B type) with three capture/compare registers each. TB0, TB1, and TB2 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-10 through Table 6-12). TB0, TB1, and TB2 have extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
RHA | RGE | DA | PW | RHA | RGE | DA | PW | |||||
21-P2.0 | 13-P2.0 | 23-P2.0 | 19-P2.0 | TB0CLK | TBCLK | Timer | N/A | N/A | ||||
ACLK (internal) | ACLK | |||||||||||
SMCLK (internal) | SMCLK | |||||||||||
21-P2.0 | 13-P2.0 | 23-P2.0 | 19-P2.0 | TB0CLK | TBCLK | |||||||
22-P2.1 | 14-P2.1 | 24-P2.1 | 20-P2.1 | TB0.0 | CCI0A | CCR0 | TB0 | TB0.0 | 22-P2.1 | 14-P2.1 | 24-P2.1 | 20-P2.1 |
17-P2.5 | N/A | 19-P2.5 | 15-P2.5 | TB0.0 | CCI0B | 17-P2.5 | N/A | 19-P2.5 | 15-P2.5 | |||
DVSS | GND | ADC10 (internal) (1)
ADC10SHSx = {2} |
ADC10 (internal) (1)
ADC10SHSx = {2} |
ADC10 (internal) (1)
ADC10SHSx = {2} |
ADC10 (internal) (1)
ADC10SHSx = {2} |
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DVCC | VCC | |||||||||||
9-P1.4 | 5-P1.4 | 13-P1.4 | 9-P1.4 | TB0.1 | CCI1A | CCR1 | TB1 | TB0.1 | 9-P1.4 | 5-P1.4 | 13-P1.4 | 9-P1.4 |
CDOUT (internal) | CCI1B | ADC10 (internal) (1)
ADC10SHSx = {3} |
ADC10 (internal) (1)
ADC10SHSx = {3} |
ADC10 (internal) (1)
ADC10SHSx = {3} |
ADC10 (internal) (1)
ADC10SHSx = {3} |
|||||||
DVSS | GND | |||||||||||
DVCC | VCC | |||||||||||
10-P1.5 | 6‑P1.5 | 14-P1.5 | 19-P1.5 | TB0.2 | CCI2A | CCR2 | TB2 | TB0.2 | 10-P1.5 | 6-P1.5 | 14-P1.5 | 19-P1.5 |
ACLK (internal) | CCI2B | |||||||||||
DVSS | GND | |||||||||||
DVCC | VCC |
INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
RHA | RGE | DA | PW | RHA | RGE | DA | PW | |||||
26-P3.6 | N/A (DVSS) | 28-P3.6 | N/A (DVSS) | TB1CLK | TBCLK | Timer | N/A | N/A | ||||
ACLK (internal) | ACLK | |||||||||||
SMCLK (internal) | SMCLK | |||||||||||
26-P3.6 | N/A (DVSS) | 28-P3.6 | N/A (DVSS) | TB1CLK | TBCLK | |||||||
23-P2.2 | N/A (DVSS) | 25-P2.2 | N/A (DVSS) | TB1.0 | CCI0A | CCR0 | TB0 | TB1.0 | 23-P2.2 | N/A | 25-P2.2 | N/A |
18-P2.6 | N/A (DVSS) | 20-P2.6 | N/A (DVSS) | TB1.0 | CCI0B | 18-P2.6 | N/A | 20-P2.6 | N/A | |||
DVSS | GND | |||||||||||
DVCC | VCC | |||||||||||
28-P1.6 | N/A (DVSS) | 30-P1.6 | N/A (DVSS) | TB1.1 | CCI1A | CCR1 | TB1 | TB1.1 | 28-P1.6 | N/A | 30-P1.6 | N/A |
24-P3.4 | N/A (DVSS) | 26-P3.4 | N/A (DVSS) | TB1.1 | CCI1B | 24-P3.4 | N/A | 26-P3.4 | N/A | |||
DVSS | GND | |||||||||||
DVCC | VCC | |||||||||||
29-P1.7 | N/A (DVSS) | 31-P1.7 | N/A (DVSS) | TB1.2 | CCI2A | CCR2 | TB2 | TB1.2 | 29-P1.7 | N/A | 31-P1.7 | N/A |
25-P3.5 | N/A (DVSS) | 27-P3.5 | N/A (DVSS) | TB1.2 | CCI2B | 25-P3.5 | N/A | 27-P3.5 | N/A | |||
DVSS | GND | |||||||||||
DVCC | VCC |
INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
RHA | RGE | DA | PW | RHA | RGE | DA | PW | |||||
24-P3.4 | N/A (DVSS) | 26-P3.4 | N/A (DVSS) | TB2CLK | TBCLK | Timer | N/A | N/A | ||||
ACLK (internal) | ACLK | |||||||||||
SMCLK (internal) | SMCLK | |||||||||||
24-P3.4 | N/A (DVSS) | 26-P3.4 | N/A (DVSS) | TB2CLK | TBCLK | |||||||
21-P2.0 | N/A (DVSS) | 23-P2.0 | N/A (DVSS) | TB2.0 | CCI0A | CCR0 | TB0 | TB2.0 | 21-P2.0 | N/A | 23-P2.0 | N/A |
15-P4.0 | N/A (DVSS) | N/A (DVSS) | N/A (DVSS) | TB2.0 | CCI0B | 15-P4.0 | N/A | 36-P4.0 | N/A | |||
DVSS | GND | |||||||||||
DVCC | VCC | |||||||||||
22-P2.1 | N/A (DVSS) | 24-P2.1 | N/A (DVSS) | TB2.1 | CCI1A | CCR1 | TB1 | TB2.1 | 22-P2.1 | N/A | 24-P2.1 | N/A |
26-P3.6 | N/A (DVSS) | 28-P3.6 | N/A (DVSS) | TB2.1 | CCI1B | 26-P3.6 | N/A | 28-P3.6 | N/A | |||
DVSS | GND | |||||||||||
DVCC | VCC | |||||||||||
23-P2.2 | N/A (DVSS) | 25-P2.2 | N/A (DVSS) | TB2.2 | CCI2A | CCR2 | TB2 | TB2.2 | 23-P2.2 | N/A | 25-P2.2 | N/A |
27-P3.7 | N/A (DVSS) | 29-P3.7 | N/A (DVSS) | TB2.2 | CCI2B | 27-P3.7 | N/A | 29-P3.7 | N/A | |||
DVSS | GND | |||||||||||
DVCC | VCC |
The ADC10_B module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and a conversion result buffer. A window comparator with lower and an upper limits allows CPU-independent result monitoring with three window comparator interrupt flags.
The primary function of the Comparator_D module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals.
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
The REF module generates all of the critical reference voltages that can be used by the various analog peripherals in the device.
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
Table 6-13 lists the base address and offset range of all available peripherals.
MODULE NAME | BASE ADDRESS | OFFSET ADDRESS RANGE |
---|---|---|
Special Functions (see Table 6-14) | 0100h | 000h–01Fh |
PMM (see Table 6-15) | 0120h | 000h–010h |
FRAM Control (see Table 6-16) | 0140h | 000h–00Fh |
CRC16 (see Table 6-17) | 0150h | 000h–007h |
Watchdog (see Table 6-18) | 015Ch | 000h–001h |
CS (see Table 6-19) | 0160h | 000h–00Fh |
SYS (see Table 6-20) | 0180h | 000h–01Fh |
Shared Reference (see Table 6-21) | 01B0h | 000h–001h |
Port P1, P2 (see Table 6-22) | 0200h | 000h–01Fh |
Port P3, P4 (see Table 6-23) | 0220h | 000h–01Fh |
Port PJ (see Table 6-24) | 0320h | 000h–01Fh |
TA0 (see Table 6-25) | 0340h | 000h–02Fh |
TA1 (see Table 6-26) | 0380h | 000h–02Fh |
TB0 (see Table 6-27) | 03C0h | 000h–02Fh |
TB1 (see Table 6-28) | 0400h | 000h–02Fh |
TB2 (see Table 6-29) | 0440h | 000h–02Fh |
Real-Time Clock (RTC_B) (see Table 6-30) | 04A0h | 000h–01Fh |
32-Bit Hardware Multiplier (see Table 6-31) | 04C0h | 000h–02Fh |
DMA General Control (see Table 6-32) | 0500h | 000h–00Fh |
DMA Channel 0 (see Table 6-32) | 0510h | 000h–00Ah |
DMA Channel 1 (see Table 6-32) | 0520h | 000h–00Ah |
DMA Channel 2 (see Table 6-32) | 0530h | 000h–00Ah |
MPU Control (see Table 6-33) | 05A0h | 000h–00Fh |
eUSCI_A0 (see Table 6-34) | 05C0h | 000h–01Fh |
eUSCI_A1 (see Table 6-35) | 05E0h | 000h–01Fh |
eUSCI_B0 (see Table 6-36) | 0640h | 000h–02Fh |
ADC10_B (see Table 6-37) | 0700h | 000h–03Fh |
Comparator_D (see Table 6-38) | 08C0h | 000h–00Fh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
SFR interrupt enable | SFRIE1 | 00h |
SFR interrupt flag | SFRIFG1 | 02h |
SFR reset pin control | SFRRPCR | 04h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
PMM Control 0 | PMMCTL0 | 00h |
PMM interrupt flags | PMMIFG | 0Ah |
PM5 control 0 | PM5CTL0 | 10h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
FRAM control 0 | FRCTLCTL0 | 00h |
General control 0 | GCCTL0 | 04h |
General control 1 | GCCTL1 | 06h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
CRC data input | CRC16DI | 00h |
CRC data input reverse byte | CRCDIRB | 02h |
CRC initialization and result | CRCINIRES | 04h |
CRC result reverse byte | CRCRESR | 06h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Watchdog timer control | WDTCTL | 00h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
CS control 0 | CSCTL0 | 00h |
CS control 1 | CSCTL1 | 02h |
CS control 2 | CSCTL2 | 04h |
CS control 3 | CSCTL3 | 06h |
CS control 4 | CSCTL4 | 08h |
CS control 5 | CSCTL5 | 0Ah |
CS control 6 | CSCTL6 | 0Ch |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
System control | SYSCTL | 00h |
JTAG mailbox control | SYSJMBC | 06h |
JTAG mailbox input 0 | SYSJMBI0 | 08h |
JTAG mailbox input 1 | SYSJMBI1 | 0Ah |
JTAG mailbox output 0 | SYSJMBO0 | 0Ch |
JTAG mailbox output 1 | SYSJMBO1 | 0Eh |
Bus Error vector generator | SYSBERRIV | 18h |
User NMI vector generator | SYSUNIV | 1Ah |
System NMI vector generator | SYSSNIV | 1Ch |
Reset vector generator | SYSRSTIV | 1Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Shared reference control | REFCTL | 00h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Port P1 input | P1IN | 00h |
Port P1 output | P1OUT | 02h |
Port P1 direction | P1DIR | 04h |
Port P1 pullup/pulldown enable | P1REN | 06h |
Port P1 selection 0 | P1SEL0 | 0Ah |
Port P1 selection 1 | P1SEL1 | 0Ch |
Port P1 interrupt vector word | P1IV | 0Eh |
Port P1 complement selection | P1SELC | 16h |
Port P1 interrupt edge select | P1IES | 18h |
Port P1 interrupt enable | P1IE | 1Ah |
Port P1 interrupt flag | P1IFG | 1Ch |
Port P2 input | P2IN | 01h |
Port P2 output | P2OUT | 03h |
Port P2 direction | P2DIR | 05h |
Port P2 pullup/pulldown enable | P2REN | 07h |
Port P2 selection 0 | P2SEL0 | 0Bh |
Port P2 selection 1 | P2SEL1 | 0Dh |
Port P2 complement selection | P2SELC | 17h |
Port P2 interrupt vector word | P2IV | 1Eh |
Port P2 interrupt edge select | P2IES | 19h |
Port P2 interrupt enable | P2IE | 1Bh |
Port P2 interrupt flag | P2IFG | 1Dh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Port P3 input | P3IN | 00h |
Port P3 output | P3OUT | 02h |
Port P3 direction | P3DIR | 04h |
Port P3 pullup/pulldown enable | P3REN | 06h |
Port P3 selection 0 | P3SEL0 | 0Ah |
Port P3 selection 1 | P3SEL1 | 0Ch |
Port P3 interrupt vector word | P3IV | 0Eh |
Port P3 complement selection | P3SELC | 16h |
Port P3 interrupt edge select | P3IES | 18h |
Port P3 interrupt enable | P3IE | 1Ah |
Port P3 interrupt flag | P3IFG | 1Ch |
Port P4 input | P4IN | 01h |
Port P4 output | P4OUT | 03h |
Port P4 direction | P4DIR | 05h |
Port P4 pullup/pulldown enable | P4REN | 07h |
Port P4 selection 0 | P4SEL0 | 0Bh |
Port P4 selection 1 | P4SEL1 | 0Dh |
Port P4 complement selection | P4SELC | 17h |
Port P4 interrupt vector word | P4IV | 1Eh |
Port P4 interrupt edge select | P4IES | 19h |
Port P4 interrupt enable | P4IE | 1Bh |
Port P4 interrupt flag | P4IFG | 1Dh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Port PJ input | PJIN | 00h |
Port PJ output | PJOUT | 02h |
Port PJ direction | PJDIR | 04h |
Port PJ pullup/pulldown enable | PJREN | 06h |
Port PJ selection 0 | PJSEL0 | 0Ah |
Port PJ selection 1 | PJSEL1 | 0Ch |
Port PJ complement selection | PJSELC | 16h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
TA0 control | TA0CTL | 00h |
Capture/compare control 0 | TA0CCTL0 | 02h |
Capture/compare control 1 | TA0CCTL1 | 04h |
Capture/compare control 2 | TA0CCTL2 | 06h |
TA0 counter | TA0R | 10h |
Capture/compare 0 | TA0CCR0 | 12h |
Capture/compare 1 | TA0CCR1 | 14h |
Capture/compare 2 | TA0CCR2 | 16h |
TA0 expansion 0 | TA0EX0 | 20h |
TA0 interrupt vector | TA0IV | 2Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
TA1 control | TA1CTL | 00h |
Capture/compare control 0 | TA1CCTL0 | 02h |
Capture/compare control 1 | TA1CCTL1 | 04h |
Capture/compare control 2 | TA1CCTL2 | 06h |
TA1 counter | TA1R | 10h |
Capture/compare 0 | TA1CCR0 | 12h |
Capture/compare 1 | TA1CCR1 | 14h |
Capture/compare 2 | TA1CCR2 | 16h |
TA1 expansion 0 | TA1EX0 | 20h |
TA1 interrupt vector | TA1IV | 2Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
TB0 control | TB0CTL | 00h |
Capture/compare control 0 | TB0CCTL0 | 02h |
Capture/compare control 1 | TB0CCTL1 | 04h |
Capture/compare control 2 | TB0CCTL2 | 06h |
TB0 counter | TB0R | 10h |
Capture/compare 0 | TB0CCR0 | 12h |
Capture/compare 1 | TB0CCR1 | 14h |
Capture/compare 2 | TB0CCR2 | 16h |
TB0 expansion 0 | TB0EX0 | 20h |
TB0 interrupt vector | TB0IV | 2Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
TB1 control | TB1CTL | 00h |
Capture/compare control 0 | TB1CCTL0 | 02h |
Capture/compare control 1 | TB1CCTL1 | 04h |
Capture/compare control 2 | TB1CCTL2 | 06h |
TB1 counter | TB1R | 10h |
Capture/compare 0 | TB1CCR0 | 12h |
Capture/compare 1 | TB1CCR1 | 14h |
Capture/compare 2 | TB1CCR2 | 16h |
TB1 expansion 0 | TB1EX0 | 20h |
TB1 interrupt vector | TB1IV | 2Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
TB2 control | TB2CTL | 00h |
Capture/compare control 0 | TB2CCTL0 | 02h |
Capture/compare control 1 | TB2CCTL1 | 04h |
Capture/compare control 2 | TB2CCTL2 | 06h |
TB2 counter | TB2R | 10h |
Capture/compare 0 | TB2CCR0 | 12h |
Capture/compare 1 | TB2CCR1 | 14h |
Capture/compare 2 | TB2CCR2 | 16h |
TB2 expansion 0 | TB2EX0 | 20h |
TB2 interrupt vector | TB2IV | 2Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
RTC control 0 | RTCCTL0 | 00h |
RTC control 1 | RTCCTL1 | 01h |
RTC control 2 | RTCCTL2 | 02h |
RTC control 3 | RTCCTL3 | 03h |
RTC prescaler 0 control | RTCPS0CTL | 08h |
RTC prescaler 1 control | RTCPS1CTL | 0Ah |
RTC prescaler 0 | RTCPS0 | 0Ch |
RTC prescaler 1 | RTCPS1 | 0Dh |
RTC interrupt vector word | RTCIV | 0Eh |
RTC seconds, RTC counter 1 | RTCSEC, RTCNT1 | 10h |
RTC minutes, RTC counter 2 | RTCMIN, RTCNT2 | 11h |
RTC hours, RTC counter 3 | RTCHOUR, RTCNT3 | 12h |
RTC day of week, RTC counter 4 | RTCDOW, RTCNT4 | 13h |
RTC days | RTCDAY | 14h |
RTC month | RTCMON | 15h |
RTC year low | RTCYEARL | 16h |
RTC year high | RTCYEARH | 17h |
RTC alarm minutes | RTCAMIN | 18h |
RTC alarm hours | RTCAHOUR | 19h |
RTC alarm day of week | RTCADOW | 1Ah |
RTC alarm days | RTCADAY | 1Bh |
Binary-to-BCD conversion register | BIN2BCD | 1Ch |
BCD-to-binary conversion register | BCD2BIN | 1Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
16-bit operand 1 – multiply | MPY | 00h |
16-bit operand 1 – signed multiply | MPYS | 02h |
16-bit operand 1 – multiply accumulate | MAC | 04h |
16-bit operand 1 – signed multiply accumulate | MACS | 06h |
16-bit operand 2 | OP2 | 08h |
16 × 16 result low word | RESLO | 0Ah |
16 × 16 result high word | RESHI | 0Ch |
16 × 16 sum extension register | SUMEXT | 0Eh |
32-bit operand 1 – multiply low word | MPY32L | 10h |
32-bit operand 1 – multiply high word | MPY32H | 12h |
32-bit operand 1 – signed multiply low word | MPYS32L | 14h |
32-bit operand 1 – signed multiply high word | MPYS32H | 16h |
32-bit operand 1 – multiply accumulate low word | MAC32L | 18h |
32-bit operand 1 – multiply accumulate high word | MAC32H | 1Ah |
32-bit operand 1 – signed multiply accumulate low word | MACS32L | 1Ch |
32-bit operand 1 – signed multiply accumulate high word | MACS32H | 1Eh |
32-bit operand 2 – low word | OP2L | 20h |
32-bit operand 2 – high word | OP2H | 22h |
32 × 32 result 0 – least significant word | RES0 | 24h |
32 × 32 result 1 | RES1 | 26h |
32 × 32 result 2 | RES2 | 28h |
32 × 32 result 3 – most significant word | RES3 | 2Ah |
MPY32 control register 0 | MPY32CTL0 | 2Ch |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
DMA channel 0 control | DMA0CTL | 00h |
DMA channel 0 source address low | DMA0SAL | 02h |
DMA channel 0 source address high | DMA0SAH | 04h |
DMA channel 0 destination address low | DMA0DAL | 06h |
DMA channel 0 destination address high | DMA0DAH | 08h |
DMA channel 0 transfer size | DMA0SZ | 0Ah |
DMA channel 1 control | DMA1CTL | 00h |
DMA channel 1 source address low | DMA1SAL | 02h |
DMA channel 1 source address high | DMA1SAH | 04h |
DMA channel 1 destination address low | DMA1DAL | 06h |
DMA channel 1 destination address high | DMA1DAH | 08h |
DMA channel 1 transfer size | DMA1SZ | 0Ah |
DMA channel 2 control | DMA2CTL | 00h |
DMA channel 2 source address low | DMA2SAL | 02h |
DMA channel 2 source address high | DMA2SAH | 04h |
DMA channel 2 destination address low | DMA2DAL | 06h |
DMA channel 2 destination address high | DMA2DAH | 08h |
DMA channel 2 transfer size | DMA2SZ | 0Ah |
DMA module control 0 | DMACTL0 | 00h |
DMA module control 1 | DMACTL1 | 02h |
DMA module control 2 | DMACTL2 | 04h |
DMA module control 3 | DMACTL3 | 06h |
DMA module control 4 | DMACTL4 | 08h |
DMA interrupt vector | DMAIV | 0Ah |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
MPU control 0 | MPUCTL0 | 00h |
MPU control 1 | MPUCTL1 | 02h |
MPU segmentation | MPUSEG | 04h |
MPU access management | MPUSAM | 06h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
eUSCI_A control word 0 | UCA0CTLW0 | 00h |
eUSCI _A control word 1 | UCA0CTLW1 | 02h |
eUSCI_A baud rate 0 | UCA0BR0 | 06h |
eUSCI_A baud rate 1 | UCA0BR1 | 07h |
eUSCI_A modulation control | UCA0MCTLW | 08h |
eUSCI_A status | UCA0STAT | 0Ah |
eUSCI_A receive buffer | UCA0RXBUF | 0Ch |
eUSCI_A transmit buffer | UCA0TXBUF | 0Eh |
eUSCI_A LIN control | UCA0ABCTL | 10h |
eUSCI_A IrDA transmit control | UCA0IRTCTL | 12h |
eUSCI_A IrDA receive control | UCA0IRRCTL | 13h |
eUSCI_A interrupt enable | UCA0IE | 1Ah |
eUSCI_A interrupt flags | UCA0IFG | 1Ch |
eUSCI_A interrupt vector word | UCA0IV | 1Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
eUSCI_A control word 0 | UCA1CTLW0 | 00h |
eUSCI _A control word 1 | UCA1CTLW1 | 02h |
eUSCI_A baud rate 0 | UCA1BR0 | 06h |
eUSCI_A baud rate 1 | UCA1BR1 | 07h |
eUSCI_A modulation control | UCA1MCTLW | 08h |
eUSCI_A status | UCA1STAT | 0Ah |
eUSCI_A receive buffer | UCA1RXBUF | 0Ch |
eUSCI_A transmit buffer | UCA1TXBUF | 0Eh |
eUSCI_A LIN control | UCA1ABCTL | 10h |
eUSCI_A IrDA transmit control | UCA1IRTCTL | 12h |
eUSCI_A IrDA receive control | UCA1IRRCTL | 13h |
eUSCI_A interrupt enable | UCA1IE | 1Ah |
eUSCI_A interrupt flags | UCA1IFG | 1Ch |
eUSCI_A interrupt vector word | UCA1IV | 1Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
eUSCI_B control word 0 | UCB0CTLW0 | 00h |
eUSCI_B control word 1 | UCB0CTLW1 | 02h |
eUSCI_B bit rate 0 | UCB0BR0 | 06h |
eUSCI_B bit rate 1 | UCB0BR1 | 07h |
eUSCI_B status word | UCB0STATW | 08h |
eUSCI_B byte counter threshold | UCB0TBCNT | 0Ah |
eUSCI_B receive buffer | UCB0RXBUF | 0Ch |
eUSCI_B transmit buffer | UCB0TXBUF | 0Eh |
eUSCI_B I2C own address 0 | UCB0I2COA0 | 14h |
eUSCI_B I2C own address 1 | UCB0I2COA1 | 16h |
eUSCI_B I2C own address 2 | UCB0I2COA2 | 18h |
eUSCI_B I2C own address 3 | UCB0I2COA3 | 1Ah |
eUSCI_B received address | UCB0ADDRX | 1Ch |
eUSCI_B address mask | UCB0ADDMASK | 1Eh |
eUSCI I2C slave address | UCB0I2CSA | 20h |
eUSCI interrupt enable | UCB0IE | 2Ah |
eUSCI interrupt flags | UCB0IFG | 2Ch |
eUSCI interrupt vector word | UCB0IV | 2Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
ADC10_B control 0 | ADC10CTL0 | 00h |
ADC10_B control 1 | ADC10CTL1 | 02h |
ADC10_B control 2 | ADC10CTL2 | 04h |
ADC10_B window comparator low threshold | ADC10LO | 06h |
ADC10_B window comparator high threshold | ADC10HI | 08h |
ADC10_B memory control 0 | ADC10MCTL0 | 0Ah |
ADC10_B conversion memory | ADC10MEM0 | 12h |
ADC10_B Interrupt enable | ADC10IE | 1Ah |
ADC10_B interrupt flags | ADC10IGH | 1Ch |
ADC10_B interrupt vector word | ADC10IV | 1Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Comparator_D control 0 | CDCTL0 | 00h |
Comparator_D control 1 | CDCTL1 | 02h |
Comparator_D control 2 | CDCTL2 | 04h |
Comparator_D control 3 | CDCTL3 | 06h |
Comparator_D interrupt | CDINT | 0Ch |
Comparator_D interrupt vector word | CDIV | 0Eh |
Figure 6-9 shows the port diagram. Table 6-39 summarizes the selection of the pin functions.
PIN NAME (P1.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P1DIR.x | P1SEL1.x | P1SEL0.x | |||
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF- | 0 | P1.0 (I/O) | I: 0; O: 1 | 0 | 0 |
TA0.CCI1A | 0 | 0 | 1 | ||
TA0.1 | 1 | ||||
DMAE0 | 0 | 1 | 0 | ||
RTCCLK | 1 | ||||
A0 (1) (3)
CD0 (1) (2) VeREF- (1) (3) |
X | 1 | 1 | ||
P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+ | 1 | P1.1 (I/O) | I: 0; O: 1 | 0 | 0 |
TA0.CCI2A | 0 | 0 | 1 | ||
TA0.2 | 1 | ||||
TA1CLK | 0 | 1 | 0 | ||
CDOUT | 1 | ||||
A1 (1) (3)
CD1 (1) (2) VeREF+ (1) (3) |
X | 1 | 1 | ||
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2 | 2 | P1.2 (I/O) | I: 0; O: 1 | 0 | 0 |
TA1.CCI1A | 0 | 0 | 1 | ||
TA1.1 | 1 | ||||
TA0CLK | 0 | 1 | 0 | ||
CDOUT | 1 | ||||
A2 (1) (3)
CD2 (1) (2) |
X | 1 | 1 |
Figure 6-10 shows the port diagram. Table 6-40 summarizes the selection of the pin functions.
PIN NAME (P1.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P1DIR.x | P1SEL1.x | P1SEL0.x | |||
P1.3/TA1.2/UCB0STE/A3/CD3 | 3 | P1.3 (I/O) | I: 0; O: 1 | 0 | 0 |
TA1.CCI2A | 0 | 0 | 1 | ||
TA1.2 | 1 | ||||
UCB0STE | X (1) | 1 | 0 | ||
A3 (3) (5)
CD3 (3) (4) |
X | 1 | 1 | ||
P1.4/TB0.1/UCA0STE/A4/CD4 | 4 | P1.4 (I/O) | I: 0; O: 1 | 0 | 0 |
TB0.CCI1A | 0 | 0 | 1 | ||
TB0.1 | 1 | ||||
UCA0STE | X (2) | 1 | 0 | ||
A4 (3) (5)
CD4 (3) (4) |
X | 1 | 1 | ||
P1.5/TB0.2/UCA0CLK/A5/CD5 | 5 | P1.5(I/O) | I: 0; O: 1 | 0 | 0 |
TB0.CCI2A | 0 | 0 | 1 | ||
TB0.2 | 1 | ||||
UCA0CLK | X (2) | 1 | 0 | ||
A5 (3) (5)
CD5 (3) (4) |
X | 1 | 1 |
Figure 6-11 shows the port diagram. Table 6-41 summarizes the selection of the pin functions.
PIN NAME (P1.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P1DIR.x | P1SEL1.x | P1SEL0.x | |||
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0 | 6 | P1.6 (I/O) | I: 0; O: 1 | 0 | 0 |
TB1.CCI1A (2) | 0 | 0 | 1 | ||
TB1.1 (2) | 1 | ||||
UCB0SIMO/UCB0SDA | X (1) | 1 | 0 | ||
TA0.CCI0A | 0 | 1 | 1 | ||
TA0.0 | 1 | ||||
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0 | 7 | P1.7 (I/O) | I: 0; O: 1 | 0 | 0 |
TB1.CCI2A (2) | 0 | 0 | 1 | ||
TB1.2 (2) | 1 | ||||
UCB0SOMI/UCB0SCL | X(1) | 1 | 0 | ||
TA1.CCI0A | 0 | 1 | 1 | ||
TA1.0 | 1 |
Figure 6-12 shows the port diagram. Table 6-42 summarizes the selection of the pin functions.
PIN NAME (P2.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P2DIR.x | P2SEL1.x | P2SEL0.x | |||
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK | 0 | P2.0 (I/O) | I: 0; O: 1 | 0 | 0 |
TB2.CCI0A (3) | 0 | 0 | 1 | ||
TB2.0 (3) | 1 | ||||
UCA0TXD/UCA0SIMO | X (1) | 1 | 0 | ||
TB0CLK | 0 | 1 | 1 | ||
ACLK | 1 | ||||
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0 | 1 | P2.1 (I/O) | I: 0; O: 1 | 0 | 0 |
TB2.CCI1A (3) | 0 | 0 | 1 | ||
TB2.1 (3) | 1 | ||||
UCA0RXD/UCA0SOMI | X (1) | 1 | 0 | ||
TB0.CCI0A | 0 | 1 | 1 | ||
TB0.0 | 1 | ||||
P2.2/TB2.2/UCB0CLK/TB1.0 | 2 | P2.2 (I/O) | I: 0; O: 1 | 0 | 0 |
TB2.CCI2A (3) | 0 | 0 | 1 | ||
TB2.2 (3) | 1 | ||||
UCB0CLK | X (2) | 1 | 0 | ||
TB1.CCI0A (3) | 0 | 1 | 1 | ||
TB1.0 (3) | 1 |
Figure 6-13 shows the port diagram. Table 6-43 summarizes the selection of the pin functions.
PIN NAME (P2.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P2DIR.x | P2SEL1.x | P2SEL0.x | |||
P2.3/TA0.0/UCA1STE/A6/CD10 | 3 | P2.3 (I/O) | I: 0; O: 1 | 0 | 0 |
TA0.CCI0B | 0 | 0 | 1 | ||
TA0.0 | 1 | ||||
UCA1STE | X (1) | 1 | 0 | ||
A6 (2) (4)
CD10 (2) (3) |
X | 1 | 1 | ||
P2.4/TA1.0/UCA1CLK/A7/CD11 | 4 | P2.4 (I/O) | I: 0; O: 1 | 0 | 0 |
TA1.CCI0B | 0 | 0 | 1 | ||
TA1.0 | 1 | ||||
UCA1CLK | X (1) | 1 | 0 | ||
A7 (2) (4)
CD11 (2) (3) |
X | 1 | 1 |
Figure 6-14 shows the port diagram. Table 6-44 summarizes the selection of the pin functions.
PIN NAME (P2.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P2DIR.x | P2SEL1.x | P2SEL0.x | |||
P2.5/TB0.0/UCA1TXD/UCA1SIMO | 5 | P2.5(I/O) (2) | I: 0; O: 1 | 0 | 0 |
TB0.CCI0B (2) | 0 | 0 | 1 | ||
TB0.0 (2) | 1 | ||||
UCA1TXD/UCA1SIMO (2) | X (1) | 1 | 0 | ||
P2.6/TB1.0/UCA1RXD/UCA1SOMI | 6 | P2.6(I/O) (2) | I: 0; O: 1 | 0 | 0 |
TB1.CCI0B (2) | 0 | 0 | 1 | ||
TB1.0 (2) | 1 | ||||
UCA1RXD/UCA1SOMI (2) | X (1) | 1 | 0 |
Figure 6-15 shows the port diagram. Table 6-45 summarizes the selection of the pin functions.
PIN NAME (P2.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P2DIR.x | P2SEL1.x | P2SEL0.x | |||
P2.7 | 7 | P2.7(I/O) (1) | I: 0; O: 1 | 0 | 0 |
Figure 6-16 shows the port diagram. Table 6-46 summarizes the selection of the pin functions.
PIN NAME (P3.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P3DIR.x | P3SEL1.x | P3SEL0.x | |||
P3.0/A12/CD12 | 0 | P3.0 (I/O) | I: 0; O: 1 | 0 | 0 |
A12 (1) (3)
CD12 (1) (2) |
X | 1 | 1 | ||
P3.1/A13/CD13 | 1 | P3.1 (I/O) | I: 0; O: 1 | 0 | 0 |
A13 (1) (3)
CD13 (1) (2) |
X | 1 | 1 | ||
P3.2/A14/CD14 | 2 | P3.2 (I/O) | I: 0; O: 1 | 0 | 0 |
A14 (1) (3)
CD14 (1) (2) |
X | 1 | 1 | ||
P3.3/A15/CD15 | 3 | P3.3 (I/O) | I: 0; O: 1 | 0 | 0 |
A15 (1) (3)
CD15 (1) (2) |
X | 1 | 1 |
Figure 6-17 shows the port diagram. Table 6-47 summarizes the selection of the pin functions.
PIN NAME (P3.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P3DIR.x | P3SEL1.x | P3SEL0.x | |||
P3.4/TB1.1/TB2CLK/SMCLK | 4 | P3.4 (I/O) (1) | I: 0; O: 1 | 0 | 0 |
TB1.CCI1B (1) | 0 | 0 | 1 | ||
TB1.1 (1) | 1 | ||||
TB2CLK (1) | 0 | 1 | 1 | ||
SMCLK (1) | 1 | ||||
P3.5/TB1.2/CDOUT | 5 | P3.5 (I/O) (1) | I: 0; O: 1 | 0 | 0 |
TB1.CCI2B (1) | 0 | 0 | 1 | ||
TB1.2 (1) | 1 | ||||
CDOUT (1) | 1 | 1 | 1 | ||
P3.6/TB2.1/TB1CLK | 6 | P3.6 (I/O) (1) | I: 0; O: 1 | 0 | 0 |
TB2.CCI1B (1) | 0 | 0 | 1 | ||
TB2.1 (1) | 1 | ||||
TB1CLK (1) | 0 | 1 | 1 |
Figure 6-18 shows the port diagram. Table 6-48 summarizes the selection of the pin functions.
Figure 6-19 shows the port diagram. Table 6-49 summarizes the selection of the pin functions.
Figure 6-20 shows the port diagram. Table 6-50 summarizes the selection of the pin functions.
PIN NAME (P4.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
---|---|---|---|---|---|
P4DIR.x | P4SEL1.x | P4SEL0.x | |||
P4.1 | 1 | P4.1 (I/O) (1) | I: 0; O: 1 | 0 | 0 |
Figure 6-21 and Figure 6-22 show the port diagrams. Table 6-51 summarizes the selection of the pin functions.
PIN NAME (PJ.x) | x | FUNCTION | CONTROL BITS OR SIGNALS(1) | ||
---|---|---|---|---|---|
PJDIR.x | PJSEL1.x | PJSEL0.x | |||
PJ.0/TDO/TB0OUTH/SMCLK/CD6 | 0 | PJ.0 (I/O) (2) | I: 0; O: 1 | 0 | 0 |
TDO (3) | X | X | X | ||
TB0OUTH | 0 | 0 | 1 | ||
SMCLK | 1 | ||||
CD6 | X | 1 | 1 | ||
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7 | 1 | PJ.1 (I/O) (2) | I: 0; O: 1 | 0 | 0 |
TDI/TCLK (3) (4) | X | X | X | ||
TB1OUTH | 0 | 0 | 1 | ||
MCLK | 1 | ||||
CD7 | X | 1 | 1 | ||
PJ.2/TMS/TB2OUTH/ACLK/CD8 | 2 | PJ.2 (I/O) (2) | I: 0; O: 1 | 0 | 0 |
TMS (3) (4) | X | X | X | ||
TB2OUTH | 0 | 0 | 1 | ||
ACLK | 1 | ||||
CD8 | X | 1 | 1 | ||
PJ.3/TCK/CD9 | 3 | PJ.3 (I/O) (2) | I: 0; O: 1 | 0 | 0 |
TCK (3) (4) | X | X | X | ||
CD9 | X | 1 | 1 |
Figure 6-23 and Figure 6-24 show the port diagrams. Table 6-52 summarizes the selection of the pin functions.
PIN NAME (P7.x) | x | FUNCTION | CONTROL BITS OR SIGNALS (1) | |||||
---|---|---|---|---|---|---|---|---|
PJDIR.x | PJSEL1.5 | PJSEL0.5 | PJSEL1.4 | PJSEL0.4 | XT1 BYPASS | |||
PJ.4/XIN | 4 | PJ.4 (I/O) | I: 0; O: 1 | X | X | 0 | 0 | X |
XIN crystal mode (2) | X | X | X | 0 | 1 | 0 | ||
XIN bypass mode (2) | X | X | X | 0 | 1 | 1 | ||
PJ.5/XOUT | 5 | PJ.5 (I/O) | I: 0; O: 1 | 0 | 0 | 0 | 0 | X |
XOUT crystal mode (2) | X | X | X | 0 | 1 | 0 | ||
PJ.5 (I/O) (3) | I: 0; O: 1 | X | X | 0 | 1 | 1 |
Table 6-53 and Table 6-54 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type.
DESCRIPTION | ADDRESS | VALUE | |||||
---|---|---|---|---|---|---|---|
FR5729 | FR5728 | FR5727 | FR5726 | FR5725 | |||
Info Block | Info length | 01A00h | 05h | 05h | 05h | 05h | 05h |
CRC length | 01A01h | 05h | 05h | 05h | 05h | 05h | |
CRC value | 01A02h | per unit | per unit | per unit | per unit | per unit | |
01A03h | per unit | per unit | per unit | per unit | per unit | ||
Device ID | 01A04h | 7Bh | 7Ah | 79h | 74h | 78h | |
Device ID | 01A05h | 80h | 80h | 80h | 81h | 80h | |
Hardware revision | 01A06h | per unit | per unit | per unit | per unit | per unit | |
Firmware revision | 01A07h | per unit | per unit | per unit | per unit | per unit | |
Die Record | Die Record Tag | 01A08h | 08h | 08h | 08h | 08h | 08h |
Die record length | 01A09h | 0Ah | 0Ah | 0Ah | 0Ah | 0Ah | |
Lot/wafer ID | 01A0Ah | per unit | per unit | per unit | per unit | per unit | |
01A0Bh | per unit | per unit | per unit | per unit | per unit | ||
01A0Ch | per unit | per unit | per unit | per unit | per unit | ||
01A0Dh | per unit | per unit | per unit | per unit | per unit | ||
Die X position | 01A0Eh | per unit | per unit | per unit | per unit | per unit | |
01A0Fh | per unit | per unit | per unit | per unit | per unit | ||
Die Y position | 01A10h | per unit | per unit | per unit | per unit | per unit | |
01A11h | per unit | per unit | per unit | per unit | per unit | ||
Test results | 01A12h | per unit | per unit | per unit | per unit | per unit | |
01A13h | per unit | per unit | per unit | per unit | per unit | ||
ADC10 Calibration | ADC10 calibration tag | 01A14h | 13h | 13h | 13h | 05h | 13h |
ADC10 calibration length | 01A15h | 10h | 10h | 10h | 10h | 10h | |
ADC gain factor | 01A16h | per unit | per unit | NA | NA | per unit | |
01A17h | per unit | per unit | NA | NA | per unit | ||
ADC offset | 01A18h | per unit | per unit | NA | NA | per unit | |
01A19h | per unit | per unit | NA | NA | per unit | ||
ADC 1.5-V reference Temp. sensor 30°C |
01A1Ah | per unit | per unit | NA | NA | per unit | |
01A1Bh | per unit | per unit | NA | NA | per unit | ||
ADC 1.5-V reference Temp. sensor 85°C |
01A1Ch | per unit | per unit | NA | NA | per unit | |
01A1Dh | per unit | per unit | NA | NA | per unit | ||
ADC 2.0-V reference Temp. sensor 30°C |
01A1Eh | per unit | per unit | NA | NA | per unit | |
01A1Fh | per unit | per unit | NA | NA | per unit | ||
ADC 2.0-V reference Temp. sensor 85°C |
01A20h | per unit | per unit | NA | NA | per unit | |
01A21h | per unit | per unit | NA | NA | per unit | ||
ADC 2.5-V reference Temp. sensor 30°C |
01A22h | per unit | per unit | NA | NA | per unit | |
01A23h | per unit | per unit | NA | NA | per unit | ||
ADC 2.5-V reference Temp. sensor 85°C |
01A24h | per unit | per unit | NA | NA | per unit | |
01A25h | per unit | per unit | NA | NA | per unit | ||
REF Calibration | REF calibration tag | 01A26h | 12h | 12h | 12h | 12h | 12h |
REF calibration length | 01A27h | 06h | 06h | 06h | 06h | 06h | |
REF 1.5-V Reference | 01A28h | per unit | per unit | per unit | per unit | per unit | |
01A29h | per unit | per unit | per unit | per unit | per unit | ||
REF 2.0-V reference | 01A2Ah | per unit | per unit | per unit | per unit | per unit | |
01A2Bh | per unit | per unit | per unit | per unit | per unit | ||
REF 2.5-V reference | 01A2Ch | per unit | per unit | per unit | per unit | per unit | |
01A2Dh | per unit | per unit | per unit | per unit | per unit |
DESCRIPTION | ADDRESS | VALUE | |||||
---|---|---|---|---|---|---|---|
FR5724 | FR5723 | FR5722 | FR5721 | FR5720 | |||
Info Block | Info length | 01A00h | 05h | 05h | 05h | 05h | 05h |
CRC length | 01A01h | 05h | 05h | 05h | 05h | 05h | |
CRC value | 01A02h | per unit | per unit | per unit | per unit | per unit | |
01A03h | per unit | per unit | per unit | per unit | per unit | ||
Device ID | 01A04h | 73h | 72h | 71h | 77h | 70h | |
Device ID | 01A05h | 81h | 81h | 81h | 80h | 81h | |
Hardware revision | 01A06h | per unit | per unit | per unit | per unit | per unit | |
Firmware revision | 01A07h | per unit | per unit | per unit | per unit | per unit | |
Die Record | Die record tag | 01A08h | 08h | 08h | 08h | 08h | 08h |
Die record length | 01A09h | 0Ah | 0Ah | 0Ah | 0Ah | 0Ah | |
Lot/wafer ID | 01A0Ah | per unit | per unit | per unit | per unit | per unit | |
01A0Bh | per unit | per unit | per unit | per unit | per unit | ||
01A0Ch | per unit | per unit | per unit | per unit | per unit | ||
01A0Dh | per unit | per unit | per unit | per unit | per unit | ||
Die X position | 01A0Eh | per unit | per unit | per unit | per unit | per unit | |
01A0Fh | per unit | per unit | per unit | per unit | per unit | ||
Die Y position | 01A10h | per unit | per unit | per unit | per unit | per unit | |
01A11h | per unit | per unit | per unit | per unit | per unit | ||
Test results | 01A12h | per unit | per unit | per unit | per unit | per unit | |
01A13h | per unit | per unit | per unit | per unit | per unit | ||
ADC10 Calibration | ADC10 calibration tag | 01A14h | 13h | 13h | 13h | 05h | 13h |
ADC10 calibration length | 01A15h | 10h | 10h | 10h | 10h | 10h | |
ADC gain factor | 01A16h | per unit | NA | NA | per unit | per unit | |
01A17h | per unit | NA | NA | per unit | per unit | ||
ADC offset | 01A18h | per unit | NA | NA | per unit | per unit | |
01A19h | per unit | NA | NA | per unit | per unit | ||
ADC 1.5-V reference Temp. sensor 30°C |
01A1Ah | per unit | NA | NA | per unit | per unit | |
01A1Bh | per unit | NA | NA | per unit | per unit | ||
ADC 1.5-V reference Temp. sensor 85°C |
01A1Ch | per unit | NA | NA | per unit | per unit | |
01A1Dh | per unit | NA | NA | per unit | per unit | ||
ADC 2.0-V reference Temp. sensor 30°C |
01A1Eh | per unit | NA | NA | per unit | per unit | |
01A1Fh | per unit | NA | NA | per unit | per unit | ||
ADC 2.0-V reference Temp. sensor 85°C |
01A20h | per unit | NA | NA | per unit | per unit | |
01A21h | per unit | NA | NA | per unit | per unit | ||
ADC 2.5-V reference Temp. sensor 30°C |
01A22h | per unit | NA | NA | per unit | per unit | |
01A23h | per unit | NA | NA | per unit | per unit | ||
ADC 2.5-V reference Temp. sensor 85°C |
01A24h | per unit | NA | NA | per unit | per unit | |
01A25h | per unit | NA | NA | per unit | per unit | ||
REF Calibration | REF calibration tag | 01A26h | 12h | 12h | 12h | 12h | 12h |
REF calibration length | 01A27h | 06h | 06h | 06h | 06h | 06h | |
REF 1.5-V reference | 01A28h | per unit | per unit | per unit | per unit | per unit | |
01A29h | per unit | per unit | per unit | per unit | per unit | ||
REF 2.0-V reference | 01A2Ah | per unit | per unit | per unit | per unit | per unit | |
01A2Bh | per unit | per unit | per unit | per unit | per unit | ||
REF 2.5-V reference | 01A2Ch | per unit | per unit | per unit | per unit | per unit | |
01A2Dh | per unit | per unit | per unit | per unit | per unit |
TI provides all of the hardware platforms and software components and tooling you need to get started today! Not only that, TI has many complementary components to meet your needs. For an overview of the MSP430™ MCU product line, the available development tools and evaluation kits, and advanced development resources, visit the MSP430 Getting Started page.
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of three prefixes: MSP, PMS, or XMS (for example, MSP430F5438A). TI recommends two of three possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications for the final device
PMS – Final silicon die that conforms to the electrical specifications for the device but has not completed quality and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI's internal qualification testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PZP) and temperature range (for example, T). Figure 7-1 provides a legend for reading the complete device name for any family member.
Table 7-1 lists the debug features supported by these microcontrollers. See the Code Composer Studio for MSP430 User's Guide for details on the available features.
MSP430 ARCHITECTURE | 4-WIRE JTAG | 2-WIRE JTAG | BREAK- POINTS (N) |
RANGE BREAK- POINTS | CLOCK CONTROL | STATE SEQUENCER | TRACE BUFFER | LPMx.5 DEBUGGING SUPPORT |
---|---|---|---|---|---|---|---|---|
MSP430Xv2 | Yes | Yes | 3 | Yes | Yes | No | No | Yes |
Design Kits and Evaluation Modules
Software
Development Tools
The following documents describe the MSP430FR572x MCUs. Copies of these documents are available on the Internet at www.ti.com.
To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (for example, MSP430FR5729). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document.
Errata
User's Guides
Application Reports
Table 7-2 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS | PRODUCT FOLDER | ORDER NOW | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
MSP430FR5729 | Click here | Click here | Click here | Click here | Click here |
MSP430FR5728 | Click here | Click here | Click here | Click here | Click here |
MSP430FR5727 | Click here | Click here | Click here | Click here | Click here |
MSP430FR5726 | Click here | Click here | Click here | Click here | Click here |
MSP430FR5725 | Click here | Click here | Click here | Click here | Click here |
MSP430FR5724 | Click here | Click here | Click here | Click here | Click here |
MSP430FR5723 | Click here | Click here | Click here | Click here | Click here |
MSP430FR5722 | Click here | Click here | Click here | Click here | Click here |
MSP430FR5721 | Click here | Click here | Click here | Click here | Click here |
MSP430FR5720 | Click here | Click here | Click here | Click here | Click here |
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
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MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks of Texas Instruments.
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TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agrees that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their systems and products, and have full and exclusive responsibility to assure the safety of their products and compliance of their products (and of all TI products used in or for such Designers’ products) with all applicable regulations, laws and other applicable requirements. Designers represent that, with respect to their applications, they have all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designers agree that prior to using or distributing any systems that include TI products, they will thoroughly test such systems and the functionality of such TI products as used in such systems.
TI’s provision of reference designs and any other technical, applications or design advice, quality characterization, reliability data or other information or services does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such reference designs or other items.
Designers are authorized to use, copy and modify any individual TI reference design only in connection with the development of end products that include the TI product(s) identified in that reference design. HOWEVER, NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of the reference design or other items described above may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
TI REFERENCE DESIGNS AND OTHER ITEMS DESCRIBED ABOVE ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING THE REFERENCE DESIGNS OR USE OF THE REFERENCE DESIGNS, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNERS AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS AS DESCRIBED IN A TI REFERENCE DESIGN OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THE REFERENCE DESIGNS OR USE OF THE REFERENCE DESIGNS, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.
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