JAJSG13G October   2012  – August 2018 MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.12.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1   Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2   Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode)
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode)
        5. Table 5-20 eUSCI (SPI Slave Mode)
        6. Table 5-21 eUSCI (I2C Mode)
      8. 5.12.8  ADC
        1. Table 5-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-23 12-Bit ADC, Timing Parameters
        3. Table 5-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 5-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 5-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 5-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 5-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 5-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 5-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 5-31 12-Bit ADC, External Reference
      9. 5.12.9  Reference
        1. Table 5-32 REF, Built-In Reference
      10. 5.12.10 Comparator
        1. Table 5-33 Comparator_E
      11. 5.12.11 FRAM
        1. Table 5-34 FRAM
    13. 5.13 Emulation and Debug
      1. Table 5-35 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
        1. 6.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM
    9. 6.9  Memory Protection Unit Including IP Encapsulation
    10. 6.10 Peripherals
      1. 6.10.1  Digital I/O
      2. 6.10.2  Oscillator and Clock System (CS)
      3. 6.10.3  Power-Management Module (PMM)
      4. 6.10.4  Hardware Multiplier (MPY)
      5. 6.10.5  Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
      6. 6.10.6  Watchdog Timer (WDT_A)
      7. 6.10.7  System Module (SYS)
      8. 6.10.8  DMA Controller
      9. 6.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.10.10 TA0, TA1
      11. 6.10.11 TA2, TA3
      12. 6.10.12 TB0
      13. 6.10.13 ADC12_B
      14. 6.10.14 Comparator_E
      15. 6.10.15 CRC16
      16. 6.10.16 AES256 Accelerator
      17. 6.10.17 True Random Seed
      18. 6.10.18 Shared Reference (REF)
      19. 6.10.19 Embedded Emulation
        1. 6.10.19.1 Embedded Emulation Module (EEM)
        2. 6.10.19.2 EnergyTrace++ Technology
      20. 6.10.20 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Capacitive Touch Functionality Ports P1, P2, P3, P4, and PJ
      2. 6.11.2  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P2 (P2.7) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      10. 6.11.10 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      11. 6.11.11 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      12. 6.11.12 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      13. 6.11.13 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
      14. 6.11.14 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      15. 6.11.15 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptor (TLV)
    13. 6.13 Identification
      1. 6.13.1 Revision Identification
      2. 6.13.2 Device Identification
      3. 6.13.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  デバイスの項目表記
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.1 Pin Diagrams

Figure 4-1 shows the 48-pin RGZ package for the MSP430FR596x and MSP430FR596x1 MCUs.

MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Wolverine_48QFN.gif

NOTE:

TI recommends connecting the QFN package pad to VSS.

NOTE:

On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX

NOTE:

On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-1 48-Pin RGZ Package (Top View) – MSP430FR596x and MSP430FR596x1

Figure 4-2 shows the 40-pin RHA package for the MSP430FR594x and MSP430FR594x1 MCUs (LFXT only).

MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Wolverine_40QFN.gif

NOTE:

TI recommends connecting the QFN package pad to VSS.

NOTE:

On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX

NOTE:

On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-2 40-Pin RHA Package (Top View) – MSP430FR594x and MSP430FR594x1

Figure 4-3 shows the 38-pin DA package for the MSP430FR594x MCUs (LFXT only).

MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Wolverine_38SSOP.gif

NOTE:

On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
Figure 4-3 38-Pin DA Package (Top View) – MSP430FR594x

Figure 4-4 shows the 40-pin RHA package for the MSP430FR595x MCUs (HFXT only).

MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 WolverineHF_40QFN.gif

NOTE:

TI recommends connecting the QFN package pad to VSS.

NOTE:

On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
Figure 4-4 40-Pin RHA Package (Top View) – MSP430FR595x

Figure 4-5 shows the 38-pin DA package for the MSP430FR595x MCUs (HFXT only).

MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 WolverineHF_38SSOP.gif

NOTE:

On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
Figure 4-5 38-Pin DA Package (Top View) – MSP430FR595x