JAJSG13G October 2012 – August 2018 MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IJTAG | Supply current adder when JTAG active (but not clocked) | 2.2 V, 3.0 V | 40 | 100 | μA | |
fSBW | Spy-Bi-Wire input frequency | 2.2 V, 3.0 V | 0 | 10 | MHz | |
tSBW,Low | Spy-Bi-Wire low clock pulse duration | 2.2 V, 3.0 V | 0.04 | 15 | μs | |
tSBW, En | Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1) | 2.2 V, 3.0 V | 110 | μs | ||
tSBW,Rst | Spy-Bi-Wire return to normal operation time | 15 | 100 | μs | ||
fTCK | TCK input frequency, 4-wire JTAG(2) | 2.2 V | 0 | 16 | MHz | |
3.0 V | 0 | 16 | MHz | |||
Rinternal | Internal pulldown resistance on TEST | 2.2 V, 3.0 V | 20 | 35 | 50 | kΩ |
fTCLK | TCLK/MCLK frequency during JTAG access, no FRAM access (limited by fSYSTEM) | 16 | MHz | |||
tTCLK,Low/High | TCLK low or high clock pulse duration, no FRAM access
|
25 | ns | |||
fTCLK,FRAM | TCLK/MCLK frequency during JTAG access, including FRAM access (limited by fSYSTEM with no FRAM wait states) | 4 | MHz | |||
tTCLK,FRAM,Low/High | TCLK low or high clock pulse duration, including FRAM accesses
|
100 | ns |