JAJSG13G October 2012 – August 2018 MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691
PRODUCTION DATA.
The BSL enables users to program the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I2C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an user-defined password. Table 6-7 list the BSL pins requirements. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see the MSP430 FRAM Device Bootloader (BSL) User's Guide.
DEVICE SIGNAL | BSL FUNCTION |
---|---|
RST/NMI/SBWTDIO | Entry sequence signal |
TEST/SBWTCK | Entry sequence signal |
P2.0 | Devices with UART BSL (FRxxxx): Data transmit |
P2.1 | Devices with UART BSL (FRxxxx): Data receive |
P1.6 | Devices with I2C BSL (FRxxxx1): Data |
P1.7 | Devices with I2C BSL (FRxxxx1): Clock |
VCC | Power supply |
VSS | Ground supply |