JAJSG24C April   2015  – August 2018 MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5922 , MSP430FR59221 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics - Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.12.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1   Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2   Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode)
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode)
        5. Table 5-20 eUSCI (SPI Slave Mode)
        6. Table 5-21 eUSCI (I2C Mode)
      8. 5.12.8  ADC12
        1. Table 5-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-23 12-Bit ADC, Timing Parameters
        3. Table 5-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 5-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 5-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 5-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 5-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 5-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 5-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 5-31 12-Bit ADC, External Reference
      9. 5.12.9  REF Module
        1. Table 5-32 REF, Built-In Reference
      10. 5.12.10 Comparator
        1. Table 5-33 Comparator_E
      11. 5.12.11 FRAM Controller
        1. Table 5-34 FRAM
      12. 5.12.12 Emulation and Debug
        1. Table 5-35 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
      2. 6.3.2 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  FRAM
    8. 6.8  RAM
    9. 6.9  Tiny RAM
    10. 6.10 Memory Protection Unit (MPU) Including IP Encapsulation
    11. 6.11 Peripherals
      1. 6.11.1  Digital I/O
      2. 6.11.2  Oscillator and Clock System (CS)
      3. 6.11.3  Power-Management Module (PMM)
      4. 6.11.4  Hardware Multiplier
      5. 6.11.5  Real-Time Clock (RTC_C)
      6. 6.11.6  Watchdog Timer (WDT_A)
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  DMA Controller
      9. 6.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.11.10 Timer_A TA0, Timer_A TA1
      11. 6.11.11 Timer_A TA2
      12. 6.11.12 Timer_A TA3
      13. 6.11.13 Timer_B TB0
      14. 6.11.14 ADC12_B
      15. 6.11.15 Comparator_E
      16. 6.11.16 CRC16
      17. 6.11.17 CRC32
      18. 6.11.18 AES256 Accelerator
      19. 6.11.19 True Random Seed
      20. 6.11.20 Shared Reference (REF_A)
      21. 6.11.21 Embedded Emulation
        1. 6.11.21.1 Embedded Emulation Module (EEM)
        2. 6.11.21.2 EnergyTrace++ Technology
      22. 6.11.22 Input/Output Diagrams
        1. 6.11.22.1  Digital I/O Functionality Port P1 to P7 and P9
        2. 6.11.22.2  Capacitive Touch Functionality on Port P1 to P7, P9, and PJ
        3. 6.11.22.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 6.11.22.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 6.11.22.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 6.11.22.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        7. 6.11.22.7  Port P4 (P4.2 to P4.7) Input/Output With Schmitt Trigger
        8. 6.11.22.8  Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
        9. 6.11.22.9  Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        10. 6.11.22.10 Port P7 (P7.0 to P7.4) Input/Output With Schmitt Trigger
        11. 6.11.22.11 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        12. 6.11.22.12 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        13. 6.11.22.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        14. 6.11.22.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  デバイスの項目表記
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.2 Pin Attributes

Table 4-1 lists the attributes of each pin.

Table 4-1 Pin Attributes

FR597x(1), FR587x(1) FR592x(1) SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE RESET STATE AFTER BOR(5)
PM, RGC PM, RGC DGG
PIN NO. PIN NO. PIN NO.
1 1 P4.3 (RD) I/O LVCMOS DVCC OFF
UCA0SOMI I/O LVCMOS DVCC –
UCA0RXD I LVCMOS DVCC –
UCB1STE I/O LVCMOS DVCC –
2 2 7 P1.4 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC –
UCA0STE I/O LVCMOS DVCC –
TA1.0 I/O LVCMOS DVCC –
3 3 8 P1.5 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC –
UCA0CLK I/O LVCMOS DVCC –
TA0.0 I/O LVCMOS DVCC –
4 4 9 P1.6 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC –
UCB0SDA I/O LVCMOS DVCC –
BSL_DAT I LVCMOS DVCC –
TA0.1 I/O LVCMOS DVCC –
5 5 10 P1.7 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC –
UCB0SCL I/O LVCMOS DVCC –
BSL_CLK I LVCMOS DVCC –
TA0.2 I/O LVCMOS DVCC –
6 6 11 DNC(6) – – – –
7 7 12 P6.0 (RD) I/O LVCMOS DVCC OFF
8 8 13 P6.1 (RD) I/O LVCMOS DVCC OFF
9 9 14 P6.2 (RD) I/O LVCMOS DVCC OFF
COUT O LVCMOS DVCC –
10 10 15 P6.3 (RD) I/O LVCMOS DVCC OFF
11 11 16 P6.4 (RD) I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC –
12 12 17 P6.5 (RD) I/O LVCMOS DVCC OFF
TB0.1 I/O LVCMOS DVCC –
13 13 18 P6.6 (RD) I/O LVCMOS DVCC OFF
TB0.2 I/O LVCMOS DVCC –
14 14 19 P3.0 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC –
TA3.2 I/O LVCMOS DVCC –
15 15 20 P3.1 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC –
UCB1SDA I/O LVCMOS DVCC –
TA3.3 I/O LVCMOS DVCC –
16 16 21 P3.2 (RD) I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC –
UCB1SCL I/O LVCMOS DVCC –
TA3.4 I/O LVCMOS DVCC –
17 17 DVSS1 P Power – N/A
18 18 DVCC1 P Power – N/A
19 19 22 TEST I LVCMOS DVCC OFF
SBWTCK I LVCMOS DVCC –
20 20 23 RST I LVCMOS DVCC OFF
NMI I LVCMOS DVCC –
SBWTDIO I/O LVCMOS DVCC –
21 21 24 PJ.0 (RD) I/O LVCMOS DVCC OFF
TDO O LVCMOS DVCC –
TB0OUTH I LVCMOS DVCC –
SMCLK O LVCMOS DVCC –
SRSCG1 O LVCMOS DVCC –
22 22 25 PJ.1 (RD) I/O LVCMOS DVCC OFF
TDI I LVCMOS DVCC –
TCLK I LVCMOS DVCC –
MCLK O LVCMOS DVCC –
SRSCG0 O LVCMOS DVCC –
23 23 26 PJ.2 (RD) I/O LVCMOS DVCC OFF
TMS I LVCMOS DVCC –
ACLK O LVCMOS DVCC –
SROSCOFF O LVCMOS DVCC –
24 24 27 PJ.3 (RD) I/O LVCMOS DVCC OFF
TCK I LVCMOS DVCC –
COUT O LVCMOS DVCC –
SRCPUOFF O LVCMOS DVCC –
25 25 28 P3.3 (RD) I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC –
TB0CLK I LVCMOS DVCC –
26 26 29 P3.4 (RD) I/O LVCMOS DVCC OFF
UCA1SIMO I/O LVCMOS DVCC –
UCA1TXD O LVCMOS DVCC –
TB0.0 I/O LVCMOS DVCC –
27 27 30 P3.5 (RD) I/O LVCMOS DVCC OFF
UCA1SOMI I/O LVCMOS DVCC –
UCA1RXD I LVCMOS DVCC –
TB0.1 I/O LVCMOS DVCC –
28 28 31 P3.6 (RD) I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC –
TB0.2 I/O LVCMOS DVCC –
29 29 32 P3.7 (RD) I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC –
TB0.3 I/O LVCMOS DVCC –
30 30 33 P2.3 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC –
TB0OUTH I LVCMOS DVCC –
31 31 34 P2.2 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC –
TB0.4 I/O LVCMOS DVCC –
RTCCLK O LVCMOS DVCC –
32 32 35 P2.1 (RD) I/O LVCMOS DVCC OFF
UCA0SOMI I/O LVCMOS DVCC –
UCA0RXD I LVCMOS DVCC –
BSL_RX I LVCMOS DVCC –
TB0.5 I/O LVCMOS DVCC –
DMAE0 I LVCMOS DVCC –
33 33 36 P2.0 (RD) I/O LVCMOS DVCC OFF
UCA0SIMO I/O LVCMOS DVCC –
UCA0TXD O LVCMOS DVCC –
BSL_TX O LVCMOS DVCC –
TB0.6 I/O LVCMOS DVCC –
TB0CLK I LVCMOS DVCC –
34 34 37 P7.0 (RD) I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC –
35 35 38 P7.1 (RD) I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC –
ACLK O LVCMOS DVCC –
36 36 39 P7.2 (RD) I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC –
37 37 40 P7.3 (RD) I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC –
38 38 41 P7.4 (RD) I/O LVCMOS DVCC OFF
SMCLK O LVCMOS DVCC –
39 39 42 DVSS2 P Power – N/A
40 40 43 DVCC2 P Power – N/A
41 41 44 P1.3 (RD) I/O LVCMOS DVCC OFF
TA1.2 I/O LVCMOS DVCC –
A3 I Analog AVCC –
C3 I Analog AVCC –
42 42 45 P1.2 (RD) I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC –
TA0CLK I LVCMOS DVCC –
COUT O LVCMOS DVCC –
A2 I Analog AVCC –
C2 I Analog AVCC –
43 43 46 P1.1 (RD) I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC –
TA1CLK I LVCMOS DVCC –
COUT O LVCMOS DVCC –
A1 I Analog AVCC –
C1 I Analog AVCC –
VREF+ O Analog AVCC –
VeREF+ I Analog – –
44 44 47 P1.0 (RD) I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC –
DMAE0 I LVCMOS DVCC –
RTCCLK O LVCMOS DVCC –
A0 I Analog AVCC –
C0 I Analog AVCC –
VREF- O Analog AVCC –
VeREF- I Analog – –
45 45 48 P9.4 (RD) I/O LVCMOS DVCC OFF
A12 I Analog AVCC –
C12 I Analog AVCC –
46 46 49 P9.5 (RD) I/O LVCMOS DVCC OFF
A13 I Analog AVCC –
C13 I Analog AVCC –
47 47 50 P9.6 (RD) I/O LVCMOS DVCC OFF
A14 I Analog AVCC –
C14 I Analog AVCC –
48 48 51 P9.7 (RD) I/O LVCMOS DVCC OFF
A15 I Analog AVCC –
C15 I Analog AVCC –
49 49 52 AVCC1 P Power – N/A
50 50 53 AVSS1 P Power – N/A
51 51 54 PJ.4 (RD) I/O LVCMOS DVCC OFF
LFXIN I Analog AVCC –
52 52 55 PJ.5 (RD) I/O LVCMOS DVCC OFF
LFXOUT O Analog AVCC –
53 53 56 AVSS2 P Power – N/A
54 PJ.7 (RD) I/O LVCMOS DVCC OFF
HFXOUT O Analog AVCC –
55 PJ.6 (RD) I/O LVCMOS DVCC OFF
HFXIN I Analog AVCC –
56 AVSS3 P Power – N/A
54 P5.4 (RD) I/O LVCMOS DVCC OFF
UCA1SIMO I/O LVCMOS DVCC –
UCA1TXD O LVCMOS DVCC –
55 P5.5 (RD) I/O LVCMOS DVCC OFF
UCA1SOMI I/O LVCMOS DVCC –
UCA1RXD I LVCMOS DVCC –
56 P5.6 (RD) I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC –
57 57 P5.7 (RD) I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC –
TB0CLK I LVCMOS DVCC –
58 58 1 P4.4 (RD) I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC –
TA1CLK I LVCMOS DVCC –
59 59 2 P4.5 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC –
TA1.0 I/O LVCMOS DVCC –
60 60 3 P4.6 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC –
UCB1SDA I/O LVCMOS DVCC –
TA1.1 I/O LVCMOS DVCC –
61 61 4 P4.7 (RD) I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC –
UCB1SCL I/O LVCMOS DVCC –
TA1.2 I/O LVCMOS DVCC –
62 62 5 DVSS3 P Power – N/A
63 63 6 DVCC3 P Power – N/A
64 64 P4.2 (RD) I/O LVCMOS DVCC OFF
UCA0SIMO I/O LVCMOS DVCC –
UCA0TXD O LVCMOS DVCC –
UCB1CLK I/O LVCMOS DVCC –
(1) Signals names with (RD) denote the reset default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
(4) To determine the pin mux encodings for each pin, see the Port I/O Diagrams section.
(5) Reset States:
OFF = High impedance with Schmitt-trigger inputs and pullup or pulldown (if available) disabled
N/A = Not applicable
(6) DNC = Do not connect