JAJSG24 データシート

JAJSG24C April 2015 – August 2018 MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5922 , MSP430FR59221 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PM|64
- MTQF008B
RGC|64
- MPQF125F

サーマルパッド・メカニカル・データ

RGC|64
- QFND102O

発注情報

3 Device Comparison

Table 3-1 and Table 3-2 summarize the available family members.

Table 3-1 Device Comparison – Family Members With UART BSL

DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	Timer_A⁽¹⁾	Timer_B⁽²⁾	eUSCI		AES	ADC12_B	I/O	PACKAGE
DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	Timer_A⁽¹⁾	Timer_B⁽²⁾	A⁽⁶⁾	B⁽⁷⁾	AES	ADC12_B	I/O	PACKAGE
MSP430FR5972	64	2	DCO HFXT LFXT	3, 3⁽³⁾ 2, 5 ⁽⁴⁾⁽⁵⁾	7	2	2	yes	8 ext	51	64 PM 64 RGC
MSP430FR5872	64	2	DCO HFXT LFXT	3, 3⁽³⁾ 2, 5 ⁽⁴⁾⁽⁵⁾	7	2	2	no	8 ext	51	64 PM 64 RGC
MSP430FR5970	32	2	DCO HFXT LFXT	3, 3⁽³⁾ 2, 5 ⁽⁴⁾⁽⁵⁾	7	2	2	yes	8 ext	51	64 PM 64 RGC
MSP430FR5922	64	2	DCO LFXT	3, 3⁽³⁾ 2, 5 ⁽⁴⁾⁽⁵⁾	7	2	2	yes	8 ext	51 46 (DGG)	64 PM 64 RGC 56 DGG
MSP430FR5870	32	2	DCO HFXT LFXT	3, 3⁽³⁾ 2, 5 ⁽⁴⁾⁽⁵⁾	7	2	2	no	8 ext	51	64 PM 64 RGC

(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(3) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.

(4) Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).

(5) Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR592x(1) with RGC and PM packages. For FR592x(1) with DGG package and all other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).

(6) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.

(7) eUSCI_B supports I²C with multiple slave addresses and SPI.

Table 3-2 Device Comparison – Family Members With I²C BSL

DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	Timer_A⁽¹⁾	Timer_B⁽²⁾	eUSCI		AES	ADC12_B	I/O	PACKAGE
DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	Timer_A⁽¹⁾	Timer_B⁽²⁾	A⁽⁶⁾	B⁽⁷⁾	AES	ADC12_B	I/O	PACKAGE
MSP430FR59721	64	2	DCO HFXT LFXT	3, 3⁽³⁾ 2, 5 ⁽⁴⁾⁽⁵⁾	7	2	2	yes	8 ext	51	64 PM 64 RGC
MSP430FR59221	64	2	DCO LFXT	3, 3⁽³⁾ 2, 5 ⁽⁴⁾⁽⁵⁾	7	2	2	yes	8 ext	51 46 (DGG)	64 PM 64 RGC 56 DGG
MSP430FR58721	64	2	DCO HFXT LFXT	3, 3⁽³⁾ 2, 5 ⁽⁴⁾⁽⁵⁾	7	2	2	no	8 ext	51	64 PM 64 RGC