JAJSG26C March   2016  – August 2018 MSP430FR5962 , MSP430FR5964 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Packaging Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. 5.12.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
        3. Table 5-10 Typical Wake-up Charge
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1   Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2   Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  LEA (Low-Energy Accelerator) (MSP430FR599x Only)
        1. Table 5-14 Low Energy Accelerator Performance
      7. 5.12.7  Timer_A and Timer_B
        1. Table 5-15 Timer_A
        2. Table 5-16 Timer_B
      8. 5.12.8  eUSCI
        1. Table 5-17 eUSCI (UART Mode) Clock Frequency
        2. Table 5-18 eUSCI (UART Mode)
        3. Table 5-19 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-20 eUSCI (SPI Master Mode)
        5. Table 5-21 eUSCI (SPI Slave Mode)
        6. Table 5-22 eUSCI (I2C Mode)
      9. 5.12.9  ADC12_B
        1. Table 5-23 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-24 12-Bit ADC, Timing Parameters
        3. Table 5-25 12-Bit ADC, Linearity Parameters
        4. Table 5-26 12-Bit ADC, Dynamic Performance With External Reference
        5. Table 5-27 12-Bit ADC, Dynamic Performance With Internal Reference
        6. Table 5-28 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. Table 5-29 12-Bit ADC, External Reference
      10. 5.12.10 Reference
        1. Table 5-30 REF, Built-In Reference
      11. 5.12.11 Comparator
        1. Table 5-31 Comparator_E
      12. 5.12.12 FRAM
        1. Table 5-32 FRAM
      13. 5.12.13 Emulation and Debug
        1. Table 5-33 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Low-Energy Accelerator (LEA) for Signal Processing (MSP430FR599x Only)
    4. 6.4  Operating Modes
      1. 6.4.1 Peripherals in Low-Power Modes
      2. 6.4.2 Idle Currents of Peripherals in LPM3 and LPM4
    5. 6.5  Interrupt Vector Table and Signatures
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM Controller A (FRCTL_A)
    9. 6.9  RAM
    10. 6.10 Tiny RAM
    11. 6.11 Memory Protection Unit (MPU) Including IP Encapsulation
    12. 6.12 Peripherals
      1. 6.12.1  Digital I/O
      2. 6.12.2  Oscillator and Clock System (CS)
      3. 6.12.3  Power-Management Module (PMM)
      4. 6.12.4  Hardware Multiplier (MPY)
      5. 6.12.5  Real-Time Clock (RTC_C)
      6. 6.12.6  Watchdog Timer (WDT_A)
      7. 6.12.7  System Module (SYS)
      8. 6.12.8  DMA Controller
      9. 6.12.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.12.10 TA0, TA1, and TA4
      11. 6.12.11 TA2 and TA3
      12. 6.12.12 TB0
      13. 6.12.13 ADC12_B
      14. 6.12.14 Comparator_E
      15. 6.12.15 CRC16
      16. 6.12.16 CRC32
      17. 6.12.17 AES256 Accelerator
      18. 6.12.18 True Random Seed
      19. 6.12.19 Shared Reference (REF)
      20. 6.12.20 Embedded Emulation
        1. 6.12.20.1 Embedded Emulation Module (EEM) (S Version)
        2. 6.12.20.2 EnergyTrace++ Technology
    13. 6.13 Input/Output Diagrams
      1. 6.13.1  Capacitive Touch Functionality on Ports P1 to P8, and PJ
      2. 6.13.2  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      3. 6.13.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.13.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      5. 6.13.5  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      6. 6.13.6  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      7. 6.13.7  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      8. 6.13.8  Port P2 (P2.7) Input/Output With Schmitt Trigger
      9. 6.13.9  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      10. 6.13.10 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      11. 6.13.11 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      12. 6.13.12 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      13. 6.13.13 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      14. 6.13.14 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      15. 6.13.15 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      16. 6.13.16 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      17. 6.13.17 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      18. 6.13.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      19. 6.13.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      20. 6.13.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    14. 6.14 Device Descriptors (TLV)
    15. 6.15 Memory Map
      1. 6.15.1 Peripheral File Map
    16. 6.16 Identification
      1. 6.16.1 Revision Identification
      2. 6.16.2 Device Identification
      3. 6.16.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  デバイスの項目表記
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.3 Signal Descriptions

Table 4-2 describes the signals for all device variants and package options.

Table 4-2 Signal Descriptions

FUNCTION SIGNAL NAME PIN NO.(1) PIN TYPE(2) DESCRIPTION
ZVW PN PM RGZ
ADC A0 A10 1 1 1 I ADC analog input A0
A1 A9 2 2 2 I ADC analog input A1
A2 B9 3 3 3 I ADC analog input A2
A3 A4 16 12 9 I ADC analog input A3
A4 B3 17 13 10 I ADC analog input A4
A5 B4 18 14 11 I ADC analog input A5
A6 J11 63 51 39 I ADC analog input A6
A7 K11 64 52 40 I ADC analog input A7
A8 F1 31 24 16 I ADC analog input A8
A9 F4 32 25 17 I ADC analog input A9
A10 G1 33 26 18 I ADC analog input A10
A11 G2 34 27 19 I ADC analog input A11
A12 A8 4 4 4 I ADC analog input A12
A13 B8 5 5 5 I ADC analog input A13
A14 B7 6 6 6 I ADC analog input A14
A15 A7 7 7 7 I ADC analog input A15
A16 E1 27 23 – I ADC analog input A16
A17 E2 28 – – I ADC analog input A17
A18 E4 29 – – I ADC analog input A18
A19 F2 30 – – I ADC analog input A19
VREF+ A9 2 2 2 O Output of positive reference voltage
VREF- A10 1 1 1 O Output of negative reference voltage
VeREF+ A9 2 2 2 I Input for an external positive reference voltage to the ADC
VeREF- A10 1 1 1 I Input for an external negative reference voltage to the ADC
BSL (I2C) BSLSCL K6 52 40 32 I/O I2C BSL clock
BSLSDA L6 51 39 31 I/O I2C BSL data
BSL (UART) BSLRX L3 42 33 25 I UART BSL receive
BSLTX L2 41 32 24 O UART BSL transmit
Clock ACLK C2
H10		 23
41
66		 19
32
54		 14
24		 O ACLK output
HFXIN H11 74 58 42 I Input for high-frequency crystal oscillator HFXT
HFXOUT G11 75 59 43 O Output for high-frequency crystal oscillator HFXT
LFXIN E11 77 61 45 I Input for low-frequency crystal oscillator LFXT
LFXOUT D11 78 62 46 O Output of low-frequency crystal oscillator LFXT
MCLK C1
G8		 22
68		 18
56		 13 O MCLK output
SMCLK B1
G10		 21
47
67		 17
35
55		 12
27		 O SMCLK output
Comparator C0 A10 1 1 1 I Comparator input C0
C1 A9 2 2 2 I Comparator input C1
C2 B9 3 3 3 I Comparator input C2
C3 A4 16 12 9 I Comparator input C3
C4 B3 17 13 10 I Comparator input C4
C5 B4 18 14 11 I Comparator input C5
C6 B1 21 17 12 I Comparator input C6
C7 C1 22 18 13 I Comparator input C7
C8 C2 23 19 14 I Comparator input C8
C9 D2 24 20 15 I Comparator input C9
C10 J11 63 51 39 I Comparator input C10
C11 K11 64 52 40 I Comparator input C11
C12 A8 4 4 4 I Comparator input C12
C13 B8 5 5 5 I Comparator input C13
C14 B7 6 6 6 I Comparator input C14
C15 A7 7 7 7 I Comparator input C15
COUT A9
B9		 2
3
48		 2
3
36		 2
3
28		 O Comparator output
DMA DMAE0 A10 1 1 1 I External DMA trigger
Debug SBWTCK H2 37 30 22 I Spy-Bi-Wire input clock
SBWTDIO J2 38 31 23 I/O Spy-Bi-Wire data input/output
SRCPUOFF D2 24 20 15 O Low-power debug: CPU Status register bit CPUOFF
SROSCOFF C2 23 19 14 O Low-power debug: CPU Status register bit OSCOFF
SRSCG0 C1 22 18 13 O Low-power debug: CPU Status register bit SCG0
SRSCG1 B1 21 17 12 O Low-power debug: CPU Status register bit SCG1
TCK D2 24 20 15 I Test clock
TCLK C1 22 18 13 I Test clock input
TDI C1 22 18 13 I Test data input
TDO B1 21 17 12 O Test data output port
TEST H2 37 30 22 I Test mode pin – select digital I/O on JTAG pins
TMS C2 23 19 14 I Test mode select
GPIO P1.0 A10 1 1 1 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P1.1 A9 2 2 2 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P1.2 B9 3 3 3 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P1.3 A4 16 12 9 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P1.4 B3 17 13 10 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P1.5 B4 18 14 11 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P1.6 L6 51 39 31 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P1.7 K6 52 40 32 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
GPIO P2.0 L2 41 32 24 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.1 L3 42 33 25 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.2 K3 43 34 26 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.3 J11 63 51 39 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.4 K11 64 52 40 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.5 G4 35 28 20 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.6 H1 36 29 21 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.7 F11 62 50 38 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
GPIO P3.0 A8 4 4 4 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P3.1 B8 5 5 5 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P3.2 B7 6 6 6 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P3.3 A7 7 7 7 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P3.4 K5 47 35 27 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P3.5 L5 48 36 28 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P3.6 H5 49 37 29 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P3.7 H6 50 38 30 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
GPIO P4.0 F1 31 24 16 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P4.1 F4 32 25 17 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P4.2 G1 33 26 18 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P4.3 G2 34 27 19 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P4.4 H7 57 45 33 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P4.5 H8 58 46 34 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P4.6 K9 59 47 35 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P4.7 D6 12 8 8 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
GPIO P5.0 L7 53 41 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P5.1 K7 54 42 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P5.2 K8 55 43 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P5.3 L8 56 44 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P5.4 J10 65 53 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P5.5 H10 66 54 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P5.6 G10 67 55 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P5.7 G8 68 56 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
GPIO P6.0 D8 8 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P6.1 D7 9 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P6.2 A6 10 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P6.3 B6 11 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P6.4 F8 69 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P6.5 F10 70 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P6.6 E8 71 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P6.7 C10 72 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
GPIO P7.0 A5 13 9 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P7.1 B5 14 10 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P7.2 D1 25 21 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P7.3 D4 26 22 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P7.4 E1 27 23 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P7.5 E2 28 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P7.6 E4 29 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P7.7 F2 30 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
GPIO P8.0 D5 15 11 – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P8.1 L4 44 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P8.2 K4 45 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
P8.3 H4 46 – – I/O General-purpose digital I/O with port interrupt and wake up from LPMx.5
GPIO PJ.0 B1 21 17 12 I/O General-purpose digital I/O
PJ.1 C1 22 18 13 I/O General-purpose digital I/O
PJ.2 C2 23 19 14 I/O General-purpose digital I/O
PJ.3 D2 24 20 15 I/O General-purpose digital I/O
PJ.4 E11 77 61 45 I/O General-purpose digital I/O
PJ.5 D11 78 62 46 I/O General-purpose digital I/O
PJ.6 H11 74 58 42 I/O General-purpose digital I/O
PJ.7 G11 75 59 43 I/O General-purpose digital I/O
I2C UCB0SCL K6 52 40 32 I/O I2C clock – eUSCI_B0 I2C mode
UCB0SDA L6 51 39 31 I/O I2C data – eUSCI_B0 I2C mode
UCB1SCL K7 54 42 – I/O I2C clock – eUSCI_B1 I2C mode
UCB1SDA L7 53 41 – I/O I2C data – eUSCI_B1 I2C mode
UCB2SCL B5 14 10 – I/O I2C clock – eUSCI_B2 I2C mode
UCB2SDA A5 13 9 – I/O I2C data – eUSCI_B2 I2C mode
UCB3SCL F10 70 – – I/O I2C clock – eUSCI_B3 I2C mode
UCB3SDA F8 69 – – I/O I2C data – eUSCI_B3 I2C mode
Power AGND B10
A11		 – – – P Analog ground
AVCC1 B11 80 64 48 P Analog power supply
AVSS1 C11 79 63 47 P Analog ground supply
AVSS2 D10 76 60 44 P Analog ground supply
AVSS3 E10 73 57 41 P Analog ground supply
DGND A1
K2
K10
L1
L11		 – – – P Digital ground
DVCC1 L10 61 49 37 P Digital power supply
DVCC2 A3 20 16 – P Digital power supply
DVCC3 K1 40 – – P Digital power supply
DVSS1 L9 60 48 36 P Digital ground supply
DVSS2 A2 19 15 – P Digital ground supply
DVSS3 J1 39 – – P Digital ground supply
QFN Pad – – – Pad P QFN package exposed thermal pad. TI recommends connection to VSS.
RTC RTCCLK A10 1 1 1 O RTC clock calibration output (not available on MSP430FR5x5x devices)
SPI UCA0CLK B4 18 14 11 I/O Clock signal input – eUSCI_A0 SPI slave mode
Clock signal output – eUSCI_A0 SPI master mode
UCA0SIMO L2 41 32 24 I/O Slave in/master out – eUSCI_A0 SPI mode
UCA0SOMI L3 42 33 25 I/O Slave out/master in – eUSCI_A0 SPI mode
UCA0STE B3 17 13 10 I/O Slave transmit enable – eUSCI_A0 SPI mode
UCA1CLK K11 64 52 40 I/O Clock signal input – eUSCI_A1 SPI slave mode
Clock signal output – eUSCI_A1 SPI master mode
UCA1SIMO G4 35 28 20 I/O Slave in/master out – eUSCI_A1 SPI mode
UCA1SOMI H1 36 29 21 I/O Slave out/master in – eUSCI_A1 SPI mode
UCA1STE J11 63 51 39 I/O Slave transmit enable – eUSCI_A1 SPI mode
UCA2CLK G10 67 55 – I/O Clock signal input – eUSCI_A2 SPI slave mode
Clock signal output – eUSCI_A2 SPI master mode
UCA2SIMO J10 65 53 – I/O Slave in/master out – eUSCI_A2 SPI mode
UCA2SOMI H10 66 54 – I/O Slave out/master in – eUSCI_A2 SPI mode
UCA2STE G8 68 56 – I/O Slave transmit enable – eUSCI_A2 SPI mode
UCA3CLK A6 10 – – I/O Clock signal input – eUSCI_A3 SPI slave mode
Clock signal output – eUSCI_A3 SPI master mode
UCA3SIMO D8 8 – – I/O Slave in/master out – eUSCI_A3 SPI mode
UCA3SOMI D7 9 – – I/O Slave out/master in – eUSCI_A3 SPI mode
UCA3STE B6 11 – – I/O Slave transmit enable – eUSCI_A3 SPI mode
UCB0CLK K3 43 34 26 I/O Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
UCB0SIMO L6 51 39 31 I/O Slave in/master out – eUSCI_B0 SPI mode
UCB0SOMI K6 52 40 32 I/O Slave out/master in – eUSCI_B0 SPI mode
UCB0STE A4 16 12 9 I/O Slave transmit enable – eUSCI_B0 SPI mode
UCB1CLK K8 55 43 – I/O Clock signal input – eUSCI_B1 SPI slave mode
Clock signal output – eUSCI_B1 SPI master mode
UCB1SIMO L7 53 41 – I/O Slave in/master out – eUSCI_B1 SPI mode
UCB1SOMI K7 54 42 – I/O Slave out/master in – eUSCI_B1 SPI mode
UCB1STE L8 56 44 – I/O Slave transmit enable – eUSCI_B1 SPI mode
UCB2CLK D1 25 21 – I/O Clock signal input – eUSCI_B2 SPI slave mode
Clock signal output – eUSCI_B2 SPI master mode
UCB2SIMO A5 13 9 – I/O Slave in/master out – eUSCI_B2 SPI mode
UCB2SOMI B5 14 10 – I/O Slave out/master in – eUSCI_B2 SPI mode
UCB2STE D4 26 22 – I/O Slave transmit enable – eUSCI_B2 SPI mode
UCB3CLK E8 71 – – I/O Clock signal input – eUSCI_B3 SPI slave mode
Clock signal output – eUSCI_B3 SPI master mode
UCB3SIMO F8 69 – – I/O Slave in/master out – eUSCI_B3 SPI mode
UCB3SOMI F10 70 – – I/O Slave out/master in – eUSCI_B3 SPI mode
UCB3STE C10 72 – – I/O Slave transmit enable – eUSCI_B3 SPI mode
System NMI J2 38 31 23 I Nonmaskable interrupt input
RST J2 38 31 23 I Reset input active low
Timer TA0.0 L6 51 39 31 I/O TA0 CCR0 capture: CCI0A input, compare: Out0
TA0.0 J11 63 51 39 I/O TA0 CCR0 capture: CCI0B input, compare: Out0
TA0.1 A10 1 1 1 I/O TA0 CCR1 capture: CCI1A input, compare: Out1
TA0.2 A9 2 2 2 I/O TA0 CCR2 capture: CCI2A input, compare: Out2
TA0CLK B9 3 3 3 I TA0 input clock
TA1.0 K6 52 40 32 I/O TA1 CCR0 capture: CCI0A input, compare: Out0
TA1.0 K11 64 52 40 I/O TA1 CCR0 capture: CCI0B input, compare: Out0
TA1.1 B9 3 3 3 I/O TA1 CCR1 capture: CCI1A input, compare: Out1
TA1.2 A4 16 12 9 I/O TA1 CCR2 capture: CCI2A input, compare: Out2
TA1CLK A9 2 2 2 I TA1 input clock
TA4.0 E1 27 23 – I/O TA4 CCR0 capture: CCI0B input, compare: Out0
TA4.0 G10 67 55 – I/O TA4 CCR0 capture: CCI0A input, compare: Out0
TA4.1 D4 26 22 – I/O TA4CCR1 capture: CCI1B input, compare: Out1
TA4.1 G8 68 56 – I/O TA4 CCR1 capture: CCI1A input, compare: Out1
TA4CLK K8 55 43 – I TA4 input clock
TB0.0 G4 35 28 20 I/O TB0 CCR0 capture: CCI0B input, compare: Out0
TB0.0 L3 42 33 25 I/O TB0 CCR0 capture: CCI0A input, compare: Out0
TB0.1 B3 17 13 10 I/O TB0 CCR1 capture: CCI1A input, compare: Out1
TB0.1 H1 36 29 21 O TB0 CCR1 compare: Out1
TB0.2 B4 18 14 11 I/O TB0 CCR2 capture: CCI2A input, compare: Out2
TB0.2 K3 43 34 26 O TB0 CCR2 compare: Out2
TB0.3 K5 47 35 27 I/O TB0 CCR3 capture: CCI3A input, compare: Out3
TB0.3 L6 51 39 31 I/O TB0 CCR3 capture: CCI3B input, compare: Out3
TB0.4 L5 48 36 28 I/O TB0 CCR4 capture: CCI4A input, compare: Out4
TB0.4 K6 52 40 32 I/O TB0 CCR4 capture: CCI4B input, compare: Out4
TB0.5 H5 49 37 29 I/O TB0 CCR5 capture: CCI5A input, compare: Out5
TB0.5 H7 57 45 33 I/O TB0CCR5 capture: CCI5B input, compare: Out5
TB0.6 L2 41 32 24 I/O TB0 CCR6 capture: CCI6B input, compare: Out6
TB0.6 H6 50 38 30 I/O TB0 CCR6 capture: CCI6A input, compare: Out6
TB0CLK L2 41 32 24 I TB0 clock input
TB0OUTH B1
J10		 21
65		 17
53		 12 I Switch all PWM outputs high impedance input – TB0
UART UCA0RXD L3 42 33 25 I Receive data – eUSCI_A0 UART mode
UCA0TXD L2 41 32 24 O Transmit data – eUSCI_A0 UART mode
UCA1RXD H1 36 29 21 I Receive data – eUSCI_A1 UART mode
UCA1TXD G4 35 28 20 O Transmit data – eUSCI_A1 UART mode
UCA2RXD H10 66 54 – I Receive data – eUSCI_A2 UART mode
UCA2TXD J10 65 53 – O Transmit data – eUSCI_A2 UART mode
UCA3RXD D7 9 – – I Receive data – eUSCI_A3 UART mode
UCA3TXD D8 8 – – O Transmit data – eUSCI_A3 UART mode
(1) N/A = not available
(2) I = input, O = output, P = power