JAJSG26C March   2016  – August 2018 MSP430FR5962 , MSP430FR5964 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Packaging Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. 5.12.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
        3. Table 5-10 Typical Wake-up Charge
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1   Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2   Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  LEA (Low-Energy Accelerator) (MSP430FR599x Only)
        1. Table 5-14 Low Energy Accelerator Performance
      7. 5.12.7  Timer_A and Timer_B
        1. Table 5-15 Timer_A
        2. Table 5-16 Timer_B
      8. 5.12.8  eUSCI
        1. Table 5-17 eUSCI (UART Mode) Clock Frequency
        2. Table 5-18 eUSCI (UART Mode)
        3. Table 5-19 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-20 eUSCI (SPI Master Mode)
        5. Table 5-21 eUSCI (SPI Slave Mode)
        6. Table 5-22 eUSCI (I2C Mode)
      9. 5.12.9  ADC12_B
        1. Table 5-23 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-24 12-Bit ADC, Timing Parameters
        3. Table 5-25 12-Bit ADC, Linearity Parameters
        4. Table 5-26 12-Bit ADC, Dynamic Performance With External Reference
        5. Table 5-27 12-Bit ADC, Dynamic Performance With Internal Reference
        6. Table 5-28 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. Table 5-29 12-Bit ADC, External Reference
      10. 5.12.10 Reference
        1. Table 5-30 REF, Built-In Reference
      11. 5.12.11 Comparator
        1. Table 5-31 Comparator_E
      12. 5.12.12 FRAM
        1. Table 5-32 FRAM
      13. 5.12.13 Emulation and Debug
        1. Table 5-33 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Low-Energy Accelerator (LEA) for Signal Processing (MSP430FR599x Only)
    4. 6.4  Operating Modes
      1. 6.4.1 Peripherals in Low-Power Modes
      2. 6.4.2 Idle Currents of Peripherals in LPM3 and LPM4
    5. 6.5  Interrupt Vector Table and Signatures
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM Controller A (FRCTL_A)
    9. 6.9  RAM
    10. 6.10 Tiny RAM
    11. 6.11 Memory Protection Unit (MPU) Including IP Encapsulation
    12. 6.12 Peripherals
      1. 6.12.1  Digital I/O
      2. 6.12.2  Oscillator and Clock System (CS)
      3. 6.12.3  Power-Management Module (PMM)
      4. 6.12.4  Hardware Multiplier (MPY)
      5. 6.12.5  Real-Time Clock (RTC_C)
      6. 6.12.6  Watchdog Timer (WDT_A)
      7. 6.12.7  System Module (SYS)
      8. 6.12.8  DMA Controller
      9. 6.12.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.12.10 TA0, TA1, and TA4
      11. 6.12.11 TA2 and TA3
      12. 6.12.12 TB0
      13. 6.12.13 ADC12_B
      14. 6.12.14 Comparator_E
      15. 6.12.15 CRC16
      16. 6.12.16 CRC32
      17. 6.12.17 AES256 Accelerator
      18. 6.12.18 True Random Seed
      19. 6.12.19 Shared Reference (REF)
      20. 6.12.20 Embedded Emulation
        1. 6.12.20.1 Embedded Emulation Module (EEM) (S Version)
        2. 6.12.20.2 EnergyTrace++ Technology
    13. 6.13 Input/Output Diagrams
      1. 6.13.1  Capacitive Touch Functionality on Ports P1 to P8, and PJ
      2. 6.13.2  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      3. 6.13.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.13.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      5. 6.13.5  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      6. 6.13.6  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      7. 6.13.7  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      8. 6.13.8  Port P2 (P2.7) Input/Output With Schmitt Trigger
      9. 6.13.9  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      10. 6.13.10 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      11. 6.13.11 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      12. 6.13.12 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      13. 6.13.13 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      14. 6.13.14 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      15. 6.13.15 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      16. 6.13.16 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      17. 6.13.17 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      18. 6.13.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      19. 6.13.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      20. 6.13.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    14. 6.14 Device Descriptors (TLV)
    15. 6.15 Memory Map
      1. 6.15.1 Peripheral File Map
    16. 6.16 Identification
      1. 6.16.1 Revision Identification
      2. 6.16.2 Device Identification
      3. 6.16.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  デバイスの項目表記
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.14 Device Descriptors (TLV)

Table 6-40 lists the contents of the device descriptor tag-length-value (TLV) structure for MSP430FR59xx(1) devices including AES. Table 6-39 summarizes the Device IDs of the MSP430FR59xx(1) devices.

Table 6-39 Device IDs

DEVICE PACKAGE DEVICE ID
01A05h 01A04h
MSP430FR5994 ZVW, PN, PM, and RGZ 0x82 0xA1
MSP430FR59941 ZVW, PN, PM, and RGZ 0x82 0xA2
MSP430FR5992 ZVW, PN, PM, and RGZ 0x82 0xA3
MSP430FR5964 ZVW, PN, PM, and RGZ 0x82 0xA4
MSP430FR5962 ZVW, PN, PM, and RGZ 0x82 0xA6

Table 6-40 Device Descriptor Table(1)

DESCRIPTION MSP430FR59xx (UART BSL) MSP430FR59941 (I2C BSL)
ADDRESS VALUE ADDRESS VALUE
Info Block Info Length 01A00h 06h 01A00h 06h
CRC Length 01A01h 06h 01A01h 06h
CRC Value 01A02h Per unit 01A02h Per unit
01A03h Per unit 01A03h Per unit
Device ID 01A04h See Table 6-39 01A04h See Table 6-39
01A05h
Hardware Revision 01A06h Per unit 01A06h Per unit
Firmware Revision 01A07h Per unit 01A07h Per unit
Die Record Die Record Tag 01A08h 08h 01A08h 08h
Die Record length 01A09h 0Ah 01A09h 0Ah
Lot/Wafer ID 01A0Ah Per unit 01A0Ah Per unit
01A0Bh Per unit 01A0Bh Per unit
01A0Ch Per unit 01A0Ch Per unit
01A0Dh Per unit 01A0Dh Per unit
Die X Position 01A0Eh Per unit 01A0Eh Per unit
01A0Fh Per unit 01A0Fh Per unit
Die Y Position 01A10h Per unit 01A10h Per unit
01A11h Per unit 01A11h Per unit
Test Results 01A12h Per unit 01A12h Per unit
01A13h Per unit 01A13h Per unit
ADC12 Calibration ADC12 Calibration Tag 01A14h 11h 01A14h 11h
ADC12 Calibration Length 01A15h 10h 01A15h 10h
ADC Gain Factor(2) 01A16h Per unit 01A16h Per unit
01A17h Per unit 01A17h Per unit
ADC Offset(3) 01A18h Per unit 01A18h Per unit
01A19h Per unit 01A19h Per unit
ADC 1.2-V Reference
Temperature Sensor 30°C		 01A1Ah Per unit 01A1Ah Per unit
01A1Bh Per unit 01A1Bh Per unit
ADC 1.2-V Reference
Temperature Sensor 85°C		 01A1Ch Per unit 01A1Ch Per unit
01A1Dh Per unit 01A1Dh Per unit
ADC 2.0-V Reference
Temperature Sensor 30°C		 01A1Eh Per unit 01A1Eh Per unit
01A1Fh Per unit 01A1Fh Per unit
ADC 2.0-V Reference
Temperature Sensor 85°C		 01A20h Per unit 01A20h Per unit
01A21h Per unit 01A21h Per unit
ADC 2.5-V Reference
Temperature Sensor 30°C		 01A22h Per unit 01A22h Per unit
01A23h Per unit 01A23h Per unit
ADC 2.5-V Reference
Temperature Sensor 85°C		 01A24h Per unit 01A24h Per unit
01A25h Per unit 01A25h Per unit
REF Calibration REF Calibration Tag 01A26h 12h 01A26h 12h
REF Calibration Length 01A27h 06h 01A27h 06h
REF 1.2-V Reference 01A28h Per unit 01A28h Per unit
01A29h Per unit 01A29h Per unit
REF 2.0-V Reference 01A2Ah Per unit 01A2Ah Per unit
01A2Bh Per unit 01A2Bh Per unit
REF 2.5-V Reference 01A2Ch Per unit 01A2Ch Per unit
01A2Dh Per unit 01A2Dh Per unit
Random Number 128-Bit Random Number Tag 01A2Eh 15h 01A2Eh 15h
Random Number Length 01A2Fh 10h 01A2Fh 10h
128-Bit Random Number(4) 01A30h Per unit 01A30h Per unit
01A31h Per unit 01A31h Per unit
01A32h Per unit 01A32h Per unit
01A33h Per unit 01A33h Per unit
01A34h Per unit 01A34h Per unit
01A35h Per unit 01A35h Per unit
01A36h Per unit 01A36h Per unit
01A37h Per unit 01A37h Per unit
01A38h Per unit 01A38h Per unit
01A39h Per unit 01A39h Per unit
01A3Ah Per unit 01A3Ah Per unit
01A3Bh Per unit 01A3Bh Per unit
01A3Ch Per unit 01A3Ch Per unit
01A3Dh Per unit 01A3Dh Per unit
01A3Eh Per unit 01A3Eh Per unit
01A3Fh Per unit 01A3Fh Per unit
BSL Configuration BSL Tag 01A40h 1Ch 01A40h 1Ch
BSL Length 01A41h 02h 01A41h 02h
BSL Interface 01A42h 00h 01A42h 01h
BSL Interface Configuration 01A43h 00h 01A43h 48h
(1) NA = Not applicable, Per unit = content can differ among individual units
(2) ADC Gain: the gain correction factor is measured at room temperature using a 2.5-V external voltage reference without internal buffer (ADC12VRSEL = 0x2, 0x4, or 0xE). Other settings (for example, using internal reference) can result in different correction factors.
(3) ADC Offset: the offset correction factor is measured at room temperature using ADC12VRSEL= 0x2 or 0x4, an external reference, VR+ = external 2.5 V, VR– = AVSS.
(4) 128-Bit Random Number: The random number is generated during production test using Microsoft's CryptGenRandom() function.