SLASEV3A March   2020  – December 2020 MSP430FR6005 , MSP430FR6007

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Current Consumption per Module
    12. 8.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. 8.13.1.1 Brownout and Device Reset Power Ramp Requirements
        2. 8.13.1.2 SVS
      2. 8.13.2  Reset Timing
        1. 8.13.2.1 Reset Input
      3. 8.13.3  Clock Specifications
        1. 8.13.3.1 Low-Frequency Crystal Oscillator, LFXT
        2. 8.13.3.2 High-Frequency Crystal Oscillator, HFXT
        3. 8.13.3.3 DCO
        4. 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.13.3.5 Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. 8.13.4.1 Wake-up Times From Low-Power Modes and Reset
        2. 8.13.4.2 Typical Wake-up Charges
        3. 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. 8.13.5.1 Digital Inputs
        2. 8.13.5.2 Digital Outputs
        3. 8.13.5.3 Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. 8.13.6.1 Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. 8.13.7.1 Timer_A
        2. 8.13.7.2 Timer_B
      8. 8.13.8  eUSCI
        1. 8.13.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
        6. 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
        7. 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
        8. 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
        9. 8.13.8.9 eUSCI (I2C Mode) Timing Diagram
      9. 8.13.9  Segment LCD Controller
        1. 8.13.9.1 LCD_C Recommended Operating Conditions
        2. 8.13.9.2 LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
        2. 8.13.10.2 12-Bit ADC, Timing Parameters
        3. 8.13.10.3 12-Bit ADC, Linearity Parameters
        4. 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
        5. 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 8.13.10.7 12-Bit ADC, External Reference
      11. 8.13.11 Reference
        1. 8.13.11.1 REF, Built-In Reference
      12. 8.13.12 Comparator
        1. 8.13.12.1 Comparator_E
      13. 8.13.13 FRAM
        1. 8.13.13.1 FRAM
      14. 8.13.14 USS
        1. 8.13.14.1 USS Recommended Operating Conditions
        2. 8.13.14.2 USS LDO
        3. 8.13.14.3 USSXTAL
        4. 8.13.14.4 USS HSPLL
        5. 8.13.14.5 USS SDHS
        6. 8.13.14.6 USS PHY Output Stage
        7. 8.13.14.7 USS PHY Input Stage, Multiplexer
        8. 8.13.14.8 USS PGA
        9. 8.13.14.9 USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. 8.13.15.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS) Module
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire (SBW) Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Watchdog Timer (WDT_A)
      7. 9.13.7  System Module (SYS)
      8. 9.13.8  DMA Controller
      9. 9.13.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 9.13.10 TA0, TA1, and TA4
      11. 9.13.11 TA2 and TA3
      12. 9.13.12 TB0
      13. 9.13.13 ADC12_B
      14. 9.13.14 USS
      15. 9.13.15 Comparator_E
      16. 9.13.16 CRC16
      17. 9.13.17 CRC32
      18. 9.13.18 AES256 Accelerator
      19. 9.13.19 True Random Seed
      20. 9.13.20 Shared Reference (REF)
      21. 9.13.21 LCD_C
      22. 9.13.22 Embedded Emulation
        1. 9.13.22.1 Embedded Emulation Module (EEM) (S Version)
        2. 9.13.22.2 EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      17. 9.14.17 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      18. 9.14.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      19. 9.14.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Detailed Design Procedure
        4. 10.2.1.4 Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.13.7 System Module (SYS)

The SYS module manages many system functions within the device. These functions include power-on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators, bootloader (BSL) entry mechanisms, and configuration management (device descriptors). The SYS module also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the application. Table 9-10 lists the SYS module interrupt vector registers.

Table 9-10 System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTERADDRESSINTERRUPT EVENTVALUEPRIORITY
SYSRSTIV, System Reset019EhNo interrupt pending00h
Brownout (BOR)02hHighest
RSTIFG RST/NMI (BOR)04h
PMMSWBOR software BOR (BOR)06h
LPMx.5 wakeup (BOR)08h
Security violation (BOR)0Ah
Reserved0Ch
SVSHIFG SVSH event (BOR)0Eh
Reserved10h
Reserved12h
PMMSWPOR software POR (POR)14h
WDTIFG watchdog time-out (PUC)16h
WDTPW password violation (PUC)18h
FRCTLPW password violation (PUC)1Ah
Uncorrectable FRAM bit error detection (PUC)1Ch
Peripheral area fetch (PUC)1Eh
PMMPW PMM password violation (PUC)20h
MPUPW MPU password violation (PUC)22h
CSPW CS password violation (PUC)24h
MPUSEGIPIFG encapsulated IP memory segment violation (PUC)26h
Reserved28h
MPUSEG1IFG segment 1 memory violation (PUC)2Ah
MPUSEG2IFG segment 2 memory violation (PUC)2Ch
MPUSEG3IFG segment 3 memory violation (PUC)2Eh
Reserved30h to 3EhLowest
SYSSNIV, System NMI019ChNo interrupt pending00h
Reserved02hHighest
Uncorrectable FRAM bit error detection04h
FRAM access time error06h
MPUSEGIPIFG encapsulated IP memory segment violation08h
Reserved0Ah
MPUSEG1IFG segment 1 memory violation0Ch
MPUSEG2IFG segment 2 memory violation0Eh
MPUSEG3IFG segment 3 memory violation10h
VMAIFG vacant memory access12h
JMBINIFG JTAG mailbox input14h
JMBOUTIFG JTAG mailbox output16h
Correctable FRAM bit error detection18h
FRAM Write Protection Detection1Ah
LEA time-out fault1Ch
LEA command fault1EhLowest
SYSUNIV, User NMI019AhNo interrupt pending00h
NMIIFG NMI pin02hHighest
OFIFG oscillator fault04h
DACCESSIFG06h
Reserved08h
Reserved0Ah to 1EhLowest