JAJSDQ7 データシート

JAJSDQ7C June 2017 – September 2018 MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PZ|100
- MTQF013A

サーマルパッド・メカニカル・データ

PZ|100
- QFND428

発注情報

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Device Comparison⁽⁷⁾⁽⁸⁾

DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	LEA	USS USSXT	MTIF	ADC12_B	Comp_E	Timer_A⁽¹⁾	Timer_B⁽²⁾	eUSCI		AES	BSL	I/Os	PACKAGE
DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	LEA	USS USSXT	MTIF	ADC12_B	Comp_E	Timer_A⁽¹⁾	Timer_B⁽²⁾	A⁽³⁾	B⁽⁴⁾	AES	BSL	I/Os	PACKAGE
MSP430FR6047	256	8	DCO HFXT LFXT	Yes	Yes	Yes	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2,2⁽⁶⁾	7	4	2	Yes	UART	76	100 PZ (LQFP)
MSP430FR60471	256	8	DCO HFXT LFXT	Yes	Yes	Yes	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2,2⁽⁶⁾	7	4	2	Yes	I²C	76	100 PZ (LQFP)
MSP430FR6037	256	8	DCO HFXT LFXT	Yes	No	Yes	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2,2⁽⁶⁾	7	4	2	Yes	UART	76	100 PZ (LQFP)
MSP430FR60371	256	8	DCO HFXT LFXT	Yes	No	Yes	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2,2⁽⁶⁾	7	4	2	Yes	I²C	76	100 PZ (LQFP)
MSP430FR6045	128	8	DCO HFXT LFXT	Yes	Yes	Yes	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2,2⁽⁶⁾	7	4	2	Yes	UART	76	100 PZ (LQFP)
MSP430FR6035	128	8	DCO HFXT LFXT	Yes	No	Yes	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2,2⁽⁶⁾	7	4	2	Yes	UART	76	100 PZ (LQFP)

(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.

(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.

(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.

(4) eUSCI_B supports I²C with multiple slave addresses and SPI.

(5) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.

(6) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any) whereas Timer TA4 provides internal, external capture/compare inputs and internal, external PWM outputs.

(7) For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.

(8) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.