JAJSDQ7 データシート

PRODUCTION DATA.

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_sdhs	SDHS power domain supply voltage	V_sdhs = V_uss		1.52	1.6	1.65	V
I_{sdhs_product}	Operating supply current into AVCC and DVCC	Includes PLL, PGA, SDHS, and DTC, modulator clock = 80 MHz, output data rate = 8 Msps			5.2		mA
f_mod	Modulator clock			68		80	MHz
BW_mod	Frequency at –3-dB SNR	Modulator clock = 80 MHz, modulator only (no filter is enabled)			1.5		MHz
SNR	Signal-to-noise ratio	Bandwidth from 200 kHz to 1.5 MHz, PGA gain: a gain from the PGA gain table for the maximum SNR	Input signal level = 1000 mVpp, PVCC = 3.0 V, f_mod = 80 MHz, OSR = 20	58.5	62.5		dB
		Bandwidth from 200 kHz to 1.5 MHz, PGA gain: a gain from the PGA gain table for the maximum SNR	Input signal level = 760 mVpp, PVCC = 2.5 V, f_mod = 80 MHz, OSR = 20	57.5	62
		Bandwidth from 200 kHz to 1.5 MHz, PGA gain: a gain from the PGA gain table for the maximum SNR	Input signal level = 200 mVpp, PVCC = 2.5 V, f_mod = 80 MHz, OSR = 20	54.5	57
		Bandwidth from 200kHz to 1.5 MHz, PGA gain: a gain from the PGA gain table for the maximum SNR	Input signal level = 100 mVpp, PVCC = 2.5 V, f_mod = 80 MHz, OSR = 20	49	53
		Bandwidth from 200 kHz to 1.5 MHz, PGA gain: a gain from the PGA gain table for the maximum SNR	Input signal level = 30 mVpp, PVCC = 2.5 V, f_mod = 80 MHz, OSR = 20	38.5	43
t_{MOD_Settle}	SDHS settling time (PGA + modulator)	TM2 – TM1, AUTOSSDIS = 0, 1% of settled DC level				40	µs
t_{MOD_Settle}	SDHS settling time (PGA + modulator)	TM2 – TM1, AUTOSSDIS = 1, 1% of settled DC level				40	µs
DROUT_sdhs	Output data rate					8	Msps

Table 5-39 lists the characteristics of the USS PHY outputs.