TYP data are based on VCC = 3.0 V and TA = 25°C (unless otherwise noted)
|
MIN |
NOM |
MAX |
UNIT |
| VCC |
Supply voltage range applied at all DVCC and AVCC pins (1) (3) (4) (2) |
1.8(7) |
|
3.6 |
V |
| VCC |
Supply voltage range applied at PVCC pin(1) |
2.2 |
|
3.6 |
V |
| VSS |
Supply voltage applied at all DVSS, AVSS, and PVSS pins. |
|
0 |
|
V |
| TA |
Operating free-air temperature |
-40 |
|
85 |
°C |
| CDVCC |
Capacitor value at DVCC(5) |
1 – 20% |
|
|
µF |
| fSYSTEM |
Processor frequency (maximum MCLK frequency)(6) |
No FRAM wait states (NWAITSx = 0) |
0 |
|
8(9) |
MHz |
| With FRAM wait states (NWAITSx = 1)(8) |
0 |
|
16(10) |
| fLEA |
LEA processor frequency |
0 |
|
16(10) |
| fACLK |
Maximum ACLK frequency |
|
|
50 |
kHz |
| fSMCLK |
Maximum SMCLK frequency |
|
|
16(10) |
MHz |
(1) TI recommends powering AVCC, DVCC, PVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference among AVCC, DVCC, PVCC must not exceed the limits specified under Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) USS module must be disabled if AVCC and DVCC are lower than 2.2 V.
(3) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for capacitor CDVCC should limit the slopes accordingly.
(4) Modules may have a different supply voltage range specification. Refer to the specification of the respective module in this data sheet.
(5) As decoupling capacitor for each supply pin pair of DVCC/ DVSS and AVCC/AVSS, place a low-ESR ceramic capacitor of 100 nF (minimum) as close as possible (few millimeters) to the respective pin pairs, for PVCC/PVSS pair, place a low-ESR ceramic capacitor of 22 uF (minimum) as close as possible (few millimeters) to the respective pin pairs.
(6) Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.
(7) The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters for the exact values.
(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always excecuted without wait states.
(9) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted.
(10) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted. If a clock source with a higher typical value is used, the clock must be divided in the clock system.