JAJSGU5 データシート

JAJSGU5B January 2019 – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PN|80
- MTQF010B

サーマルパッド・メカニカル・データ

発注情報

8.13.15.1 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		V_CC	MIN	TYP	MAX	UNIT
I_JTAG	Supply current adder when JTAG active (but not clocked)	2.2 V, 3.0 V		40	100	μA
f_SBW	Spy-Bi-Wire input frequency	2.2 V, 3.0 V	0		10	MHz
t_SBW,Low	Spy-Bi-Wire low clock pulse duration	2.2 V, 3.0 V	0.04		15	μs
t_{SBW, En}	Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾	2.2 V, 3.0 V			110	μs
t_SBW,Rst	Spy-Bi-Wire return to normal operation time		15		100	μs
f_TCK	TCK input frequency, 4-wire JTAG⁽²⁾	2.2 V	0		16	MHz
f_TCK	TCK input frequency, 4-wire JTAG⁽²⁾	3.0 V	0		16	MHz
R_internal	Internal pulldown resistance on TEST	2.2 V, 3.0 V	20	35	50	kΩ
f_TCLK	TCLK/MCLK frequency during JTAG access, no FRAM access (limited by f_SYSTEM)				16	MHz
t_{TCLK,Low/High}	TCLK low or high clock pulse duration, no FRAM access				25	ns
f_TCLK,FRAM	TCLK/MCLK frequency during JTAG access, including FRAM access (limited by f_SYSTEM with no FRAM wait states)				4	MHz
t_{TCLK,FRAM, Low/High}	TCLK low or high clock pulse duration, including FRAM accesses				100	ns

(1) Tools that access the Spy-Bi-Wire and the BSL interfaces must wait for the t_SBW,En time after the first transition of the TEST/SBWTCK pin (low to high), before the second transition of the pin (high to low) during the entry sequence.

(2) f_TCK may be restricted to meet the timing requirements of the module selected.