JAJSDQ7C June   2017  – September 2018 MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charges
        3. 5.13.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.13.5.1   Typical Characteristics, Digital Outputs
      6. 5.13.6  LEA
        1. Table 5-13 Low-Energy Accelerator (LEA) Performance
      7. 5.13.7  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      8. 5.13.8  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-20 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-21 eUSCI (I2C Mode) Switching Characteristics
      9. 5.13.9  Segment LCD Controller
        1. Table 5-22 LCD_C Recommended Operating Conditions
        2. Table 5-23 LCD_C Electrical Characteristics
      10. 5.13.10 ADC12_B
        1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-25 12-Bit ADC, Timing Parameters
        3. Table 5-26 12-Bit ADC, Linearity Parameters
        4. Table 5-27 12-Bit ADC, Dynamic Performance With External Reference
        5. Table 5-28 12-Bit ADC, Dynamic Performance With Internal Reference
        6. Table 5-29 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. Table 5-30 12-Bit ADC, External Reference
      11. 5.13.11 Reference
        1. Table 5-31 REF, Built-In Reference
      12. 5.13.12 Comparator
        1. Table 5-32 Comparator_E
      13. 5.13.13 FRAM
        1. Table 5-33 FRAM
      14. 5.13.14 USS
        1. Table 5-34 USS Recommended Operating Conditions
        2. Table 5-35 USS LDO
        3. Table 5-36 USSXTAL
        4. Table 5-37 USS HSPLL
        5. Table 5-38 USS SDHS
        6. Table 5-39 USS PHY Output Stage
        7. Table 5-40 USS PHY Input Stage, Multiplexer
        8. Table 5-41 USS PGA
        9. Table 5-42 USS Bias Voltage Generator
      15. 5.13.15 Emulation and Debug
        1. Table 5-43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Ultrasonic Sensing Solution (USS) Module
    4. 6.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 6.5  Operating Modes
      1. 6.5.1 Peripherals in Low-Power Modes
      2. 6.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 6.6  Interrupt Vector Table and Signatures
    7. 6.7  Bootloader (BSL)
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire (SBW) Interface
    9. 6.9  FRAM Controller A (FRCTL_A)
    10. 6.10 RAM
    11. 6.11 Tiny RAM
    12. 6.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 6.13 Peripherals
      1. 6.13.1  Digital I/O
      2. 6.13.2  Oscillator and Clock System (CS)
      3. 6.13.3  Power-Management Module (PMM)
      4. 6.13.4  Hardware Multiplier (MPY)
      5. 6.13.5  Real-Time Clock (RTC_C)
      6. 6.13.6  Measurement Test Interface (MTIF)
      7. 6.13.7  Watchdog Timer (WDT_A)
      8. 6.13.8  System Module (SYS)
      9. 6.13.9  DMA Controller
      10. 6.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 6.13.11 TA0, TA1, and TA4
      12. 6.13.12 TA2 and TA3
      13. 6.13.13 TB0
      14. 6.13.14 ADC12_B
      15. 6.13.15 USS
      16. 6.13.16 Comparator_E
      17. 6.13.17 CRC16
      18. 6.13.18 CRC32
      19. 6.13.19 AES256 Accelerator
      20. 6.13.20 True Random Seed
      21. 6.13.21 Shared Reference (REF)
      22. 6.13.22 LCD_C
      23. 6.13.23 Embedded Emulation
        1. 6.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 6.13.23.2 EnergyTrace++ Technology
    14. 6.14 Input/Output Diagrams
      1. 6.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 6.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 6.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 6.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 6.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 6.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 6.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 6.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 6.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 6.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 6.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 6.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 6.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger
      14. 6.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger
      15. 6.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
      16. 6.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      17. 6.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      18. 6.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      19. 6.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      20. 6.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      21. 6.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 6.15 Device Descriptors (TLV)
    16. 6.16 Memory Map
      1. 6.16.1 Peripheral File Map
    17. 6.17 Identification
      1. 6.17.1 Revision Identification
      2. 6.17.2 Device Identification
      3. 6.17.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2  External Oscillator (HFXT and LFXT)
      3. 7.1.3  USS Oscillator (USSXT)
      4. 7.1.4  Transducer Connection to the USS Module
      5. 7.1.5  Charge Pump Control of Input Multiplexer
      6. 7.1.6  JTAG
      7. 7.1.7  Reset
      8. 7.1.8  Unused Pins
      9. 7.1.9  General Layout Recommendations
      10. 7.1.10 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 使い始めと次の手順
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.2 Pin Attributes

Table 4-1 lists the attributes of each pin.

Table 4-1 Pin Attributes

PIN NUMBER SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE(5) RESET STATE AFTER BOR(7)
1 P2.2 I/O LVCMOS DVCC OFF
COUT O LVCMOS DVCC –
UCA0CLK I/O LVCMOS DVCC –
A14 I Analog DVCC –
C14 I Analog DVCC –
2 P2.3 I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC –
UCA0STE I/O LVCMOS DVCC –
A15 I Analog DVCC –
C15 I Analog DVCC –
3 P1.0 I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC –
TA1.0 I/O LVCMOS DVCC –
A0 I Analog DVCC –
C0 I Analog DVCC –
VREF- O Analog DVCC –
VeREF- I Analog DVCC –
4 P1.1 I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC –
TA4.0 I/O LVCMOS DVCC –
A1 I Analog DVCC –
C1 I Analog DVCC –
VREF+ O Analog DVCC –
VeREF+ I Analog DVCC –
5 AVSS2 P Power – N/A
6 PJ.4 I/O LVCMOS DVCC OFF
LFXIN I Analog DVCC –
7 PJ.5 I/O LVCMOS DVCC OFF
LFXOUT O Analog DVCC –
8 AVSS3 P Power – N/A
9 PJ.6 I/O LVCMOS DVCC –
HFXIN I Analog DVCC –
10 PJ.7 I/O LVCMOS DVCC OFF
HFXOUT O Analog DVCC –
11 AVSS4 P Power – N/A
12 P1.4 I/O LVCMOS DVCC OFF
TB0.4 I/O LVCMOS DVCC –
UCB0STE I/O LVCMOS DVCC –
A2 I Analog DVCC –
C2 I Analog DVCC –
13 P1.5 I/O LVCMOS DVCC OFF
TB0.5 I/O LVCMOS DVCC –
UCB0CLK I/O LVCMOS DVCC –
A3 I Analog DVCC –
C3 I Analog DVCC –
14 P1.6 I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC –
UCB0SDA I/O LVCMOS DVCC –
A4 I Analog DVCC –
C4 I Analog DVCC –
15 P1.7 I/O LVCMOS DVCC OFF
USSTRG I LVCMOS DVCC –
UCB0SOMI I/O LVCMOS DVCC –
UCB0SCL I/O LVCMOS DVCC –
A5 I Analog DVCC –
C5 I Analog DVCC –
16 P2.0 I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
A6 I Analog DVCC –
C6 I Analog DVCC –
17 P2.1 I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
A7 I Analog DVCC –
C7 I Analog DVCC –
18 P1.2 I/O LVCMOS DVCC OFF
UCA1TXD O LVCMOS DVCC –
UCA1SIMO I/O LVCMOS DVCC –
A8 I Analog DVCC –
C8 I Analog DVCC –
19 P1.3 I/O LVCMOS DVCC OFF
UCA1RXD I LVCMOS DVCC –
UCA1SOMI I/O LVCMOS DVCC –
A9 I Analog DVCC –
C9 I Analog DVCC –
20 TEST I LVCMOS DVCC PD
SBWTCK I LVCMOS DVCC –
21 RST I/O LVCMOS DVCC PU
NMI I LVCMOS DVCC –
SBWTDIO I/O LVCMOS DVCC –
22 PJ.0 I/O LVCMOS DVCC OFF
TDO O LVCMOS DVCC –
ACLK O LVCMOS DVCC –
SRSCG1 O LVCMOS DVCC –
DMAE0 I LVCMOS DVCC –
C10 I Analog DVCC –
23 PJ.1 I/O LVCMOS DVCC OFF
TDI I LVCMOS DVCC –
TCLK I LVCMOS DVCC –
SMCLK O LVCMOS DVCC –
SRSCG0 O LVCMOS DVCC –
TA4CLK I LVCMOS DVCC –
C11 I Analog DVCC –
24 PJ.2 I/O LVCMOS DVCC OFF
TMS I LVCMOS DVCC –
MCLK O LVCMOS DVCC –
SROSCOFF O LVCMOS DVCC –
TB0OUTH I LVCMOS DVCC –
C12 I Analog DVCC –
25 PJ.3 I/O LVCMOS DVCC OFF
TCK I LVCMOS DVCC –
RTCCLK O LVCMOS DVCC –
SRCPUOFF O LVCMOS DVCC –
TB0.6 I/O LVCMOS DVCC –
C13 I Analog DVCC –
26 DVSS1 P Power – N/A
27 DVCC1 P Power – N/A
28 P2.4 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC –
TB0CLK I LVCMOS DVCC –
TA1CLK I LVCMOS DVCC –
S32 O Analog DVCC –
29 P2.5 I/O LVCMOS DVCC OFF
TA4.0 I/O LVCMOS DVCC –
S31 O Analog DVCC –
30 P2.6 I/O LVCMOS DVCC OFF
TA4.1 I/O LVCMOS DVCC –
S30 O Analog DVCC –
31 P3.0 I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC –
S29 O Analog DVCC –
32 P3.1 I/O LVCMOS DVCC OFF
TB0.1 O LVCMOS DVCC –
S28 O Analog DVCC –
33 P3.2 I/O LVCMOS DVCC OFF
TB0.2 O LVCMOS DVCC –
S27 O Analog DVCC –
34 P3.3 I/O LVCMOS DVCC OFF
TB0.3 I/O LVCMOS DVCC –
S26 O Analog DVCC –
35 P3.4 I/O LVCMOS DVCC OFF
TB0OUTH I LVCMOS DVCC –
S25 O Analog DVCC –
36 P3.5 I/O LVCMOS DVCC OFF
TB0.4 I/O LVCMOS DVCC –
S24 O Analog DVCC –
37 P3.6 I/O LVCMOS DVCC OFF
TB0.5 I/O LVCMOS DVCC –
S23 O Analog DVCC –
38 P3.7 I/O LVCMOS DVCC OFF
TB0.6 I/O LVCMOS DVCC –
S22 O Analog DVCC –
39 P2.7 I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC –
S21 O Analog DVCC –
40 P9.0 I/O LVCMOS DVCC OFF
TA1.0 I/O LVCMOS DVCC –
S20 O Analog DVCC –
41 P9.1 I/O LVCMOS DVCC OFF
SMCLK O LVCMOS DVCC –
S19 O Analog DVCC –
42 P9.2 I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC –
S18 O Analog DVCC –
43 P9.3 I/O LVCMOS DVCC OFF
ACLK O LVCMOS DVCC –
S17 O Analog DVCC –
44 P4.0 I/O LVCMOS DVCC OFF
RTCCLK O LVCMOS DVCC –
S16 O Analog DVCC –
45 P4.1 I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC –
S15 O Analog DVCC –
46 P4.2 I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC –
S14 O Analog DVCC –
47 P4.3 I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
S13 O Analog DVCC –
48 P4.4 I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
S12 O Analog DVCC –
49 P4.5 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC –
TA1CLK I LVCMOS DVCC –
S11 O Analog DVCC –
50 P4.6 I/O LVCMOS DVCC OFF
TB0CLK I LVCMOS DVCC –
TA4CLK I LVCMOS DVCC –
S10 O Analog DVCC –
51 DVSS2 P Power – N/A
52 DVCC2 P Power – N/A
53 P4.7 I/O LVCMOS DVCC OFF
DMAE0 I LVCMOS DVCC –
S9 O Analog DVCC –
54 P5.0 I/O LVCMOS DVCC OFF
UCA2TXD O LVCMOS DVCC –
UCA2SIMO I/O LVCMOS DVCC –
S8 O Analog DVCC –
55 P5.1 I/O LVCMOS DVCC OFF
UCA2RXD I LVCMOS DVCC –
UCA2SOMI I/O LVCMOS DVCC –
S7 O Analog DVCC –
56 P5.2 I/O LVCMOS DVCC OFF
UCA2CLK I/O LVCMOS DVCC –
S6 O Analog DVCC –
57 P5.3 I/O LVCMOS DVCC OFF
UCA2STE I/O LVCMOS DVCC –
S5 O Analog DVCC –
58 P5.4 I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC –
S4 O Analog DVCC –
59 P5.5 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC –
UCB1SIMO I/O LVCMOS DVCC –
UCB1SDA I/O LVCMOS DVCC –
S3 O Analog DVCC –
60 P5.6 I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC –
UCB1SCL I/O LVCMOS DVCC –
S2 O Analog DVCC –
61 P5.7 I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC –
S1 O Analog DVCC –
62 P6.0 I/O LVCMOS DVCC OFF
COUT I LVCMOS DVCC –
S0 O Analog DVCC –
63 P6.4 I/O LVCMOS DVCC OFF
COM0 O Analog DVCC –
64 P6.5 I/O LVCMOS DVCC OFF
COM1 O Analog DVCC –
65 P6.6 I/O LVCMOS DVCC OFF
COM2 O Analog DVCC –
S38 O Analog DVCC –
66 P6.7 I/O LVCMOS DVCC OFF
COM3 O Analog DVCC –
S37 O Analog DVCC –
67 P7.0 I/O LVCMOS DVCC OFF
UCA2TXD O LVCMOS DVCC –
UCA2SIMO I/O LVCMOS DVCC –
ACLK O LVCMOS DVCC –
COM4 O Analog DVCC –
S36 O Analog DVCC –
68 P7.1 I/O LVCMOS DVCC OFF
UCA2RXD I LVCMOS DVCC –
UCA2SOMI I/O LVCMOS DVCC –
SMCLK O LVCMOS DVCC –
COM5 O Analog DVCC –
S35 O Analog DVCC –
69 P7.2 I/O LVCMOS DVCC OFF
UCA2CLK I/O LVCMOS DVCC –
TB0.0 I/O LVCMOS DVCC –
COM6 O Analog DVCC –
S34 O Analog DVCC –
70 P7.3 I/O LVCMOS DVCC OFF
UCA2STE I/O LVCMOS DVCC –
TB0.1 I/O LVCMOS DVCC –
COM7 O Analog DVCC –
S33 O Analog DVCC –
71 P6.1 I/O LVCMOS DVCC OFF
R03 I/O Analog DVCC –
72 P6.2 I/O LVCMOS DVCC OFF
R13 I/O Analog DVCC –
LCDREF I Analog - –
73 P6.3 I/O LVCMOS DVCC OFF
R23 I/O Analog DVCC –
74 R33 I/O Analog DVCC -
LCDCAP I/O Analog DVCC –
75 DVSS3 P Power – N/A
76 DVCC3 P Power – N/A
77 P7.4 I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC –
MTIF_OUT_IN I/O LVCMOS DVCC –
78 P7.5 I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC –
MTIF_PIN_EN I LVCMOS DVCC –
79 P8.0 I/O LVCMOS DVCC OFF
UCA3STE I/O LVCMOS DVCC –
TB0.2 I/O LVCMOS DVCC –
DMAE0 I LVCMOS DVCC –
80 P8.1 I/O LVCMOS DVCC OFF
UCA3CLK I/O LVCMOS DVCC –
TB0.3 I/O LVCMOS DVCC –
TB0OUTH I LVCMOS DVCC –
81 P8.2 I/O LVCMOS DVCC OFF
UCA3RXD O LVCMOS DVCC –
UCA3SOMI I/O LVCMOS DVCC –
MCLK O LVCMOS DVCC –
82 P8.3 I/O LVCMOS DVCC OFF
UCA3TXD O LVCMOS DVCC –
UCA3SIMO I/O LVCMOS DVCC –
RTCCLK O LVCMOS DVCC –
83 P7.6 I/O LVCMOS DVCC OFF
TA4.1 I/O LVCMOS DVCC –
DMAE0 I LVCMOS DVCC –
COUT O LVCMOS DVCC –
84 P7.7 I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC –
TB0OUTH I LVCMOS DVCC –
COUT O LVCMOS DVCC –
85 CH1_IN I Analog PVCC –
86 CH1_OUT O Analog PVCC –
87 PVSS P Power – N/A
88 PVCC P Power – N/A
89 PVSS P Power – N/A
90 CH0_OUT O Analog PVCC –
91 CH0_IN I Analog PVCC –
92 P8.4 I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC –
TA1.2 I/O LVCMOS DVCC –
A10 I Analog DVCC –
93 P8.5 I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC –
UCB1SDA I/O LVCMOS DVCC –
A11 I Analog DVCC –
94 P8.6 I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC –
UCB1SCL I/O LVCMOS DVCC –
A12 I Analog DVCC –
95 P8.7 I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC –
USSXT_BOUT I/O LVCMOS DVCC –
A13 I Analog DVCC –
96 AVSS5 P Power – N/A
97 USSXTIN(6) I Analog 1.5V –
98 USSXTOUT(6) O Analog 1.5V –
99 AVSS1 P Power – N/A
100 AVCC1 P Power – N/A
(1) The signal that is listed first for each pin is the reset default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
(4) To determine the pin mux encodings for each pin, see Section 6.14.
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Do not connect USSXTIN and USSXTOUT pins to AVCC nor to DVCC. USSXTIN does not support bypass mode, so do not drive an external clock on the USSXTIN pin.
(7) Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable