JAJSG20C August   2014  – August 2018 MSP430FR6877 , MSP430FR6879 , MSP430FR68791

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions – MSP430FR687x and MSP430FR687x1
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1 Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2 Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3 Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4 Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.13.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5 Peripherals
        1. 5.13.5.1 Digital I/Os
          1. Table 5-11 Digital Inputs
          2. Table 5-12 Digital Outputs
          3. 5.13.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
          4. Table 5-13 Pin-Oscillator Frequency, Ports Px
          5. 5.13.5.1.2 Typical Characteristics, Pin-Oscillator Frequency
        2. 5.13.5.2 Timer_A and Timer_B
          1. Table 5-14 Timer_A
          2. Table 5-15 Timer_B
        3. 5.13.5.3 eUSCI
          1. Table 5-16 eUSCI (UART Mode) Clock Frequency
          2. Table 5-17 eUSCI (UART Mode)
          3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
          4. Table 5-19 eUSCI (SPI Master Mode)
          5. Table 5-20 eUSCI (SPI Slave Mode)
          6. Table 5-21 eUSCI (I2C Mode)
        4. 5.13.5.4 LCD Controller
          1. Table 5-22 LCD_C, Recommended Operating Conditions
          2. Table 5-23 LCD_C Electrical Characteristics
        5. 5.13.5.5 ADC
          1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
          2. Table 5-25 12-Bit ADC, Timing Parameters
          3. Table 5-26 12-Bit ADC, Linearity Parameters With External Reference
          4. Table 5-27 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
          5. Table 5-28 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
          6. Table 5-29 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
          7. Table 5-30 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
          8. Table 5-31 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
          9. Table 5-32 12-Bit ADC, Temperature Sensor and Built-In V1/2
          10. Table 5-33 12-Bit ADC, External Reference
        6. 5.13.5.6 Reference
          1. Table 5-34 REF, Built-In Reference
        7. 5.13.5.7 Comparator
          1. Table 5-35 Comparator_E
        8. 5.13.5.8 FRAM Controller
          1. Table 5-36 FRAM
      6. 5.13.6 Emulation and Debug
        1. Table 5-37 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
        1. 6.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  FRAM
    8. 6.8  RAM
    9. 6.9  Tiny RAM
    10. 6.10 Memory Protection Unit Including IP Encapsulation
    11. 6.11 Peripherals
      1. 6.11.1  Digital I/O
      2. 6.11.2  Oscillator and Clock System (CS)
      3. 6.11.3  Power-Management Module (PMM)
      4. 6.11.4  Hardware Multiplier (MPY)
      5. 6.11.5  Real-Time Clock (RTC_C)
      6. 6.11.6  Watchdog Timer (WDT_A)
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  DMA Controller
      9. 6.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.11.10 Timer_A TA0, Timer_A TA1
      11. 6.11.11 Timer_A TA2
      12. 6.11.12 Timer_A TA3
      13. 6.11.13 Timer_B TB0
      14. 6.11.14 ADC12_B
      15. 6.11.15 Comparator_E
      16. 6.11.16 CRC16
      17. 6.11.17 CRC32
      18. 6.11.18 True Random Seed
      19. 6.11.19 Shared Reference (REF_A)
      20. 6.11.20 LCD_C
      21. 6.11.21 Embedded Emulation
        1. 6.11.21.1 Embedded Emulation Module (EEM)
        2. 6.11.21.2 EnergyTrace++™ Technology
      22. 6.11.22 Input/Output Diagrams
        1. 6.11.22.1  Digital I/O Functionality – Ports P1 to P10
        2. 6.11.22.2  Capacitive Touch Functionality Ports P1 to P10 and PJ
        3. 6.11.22.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 6.11.22.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 6.11.22.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 6.11.22.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
        7. 6.11.22.7  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        8. 6.11.22.8  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
        9. 6.11.22.9  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
        10. 6.11.22.10 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        11. 6.11.22.11 Port P6 (P6.7) Input/Output With Schmitt Trigger
        12. 6.11.22.12 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger
        13. 6.11.22.13 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
        14. 6.11.22.14 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
        15. 6.11.22.15 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
        16. 6.11.22.16 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        17. 6.11.22.17 Port P10 (P10.0 to P10.2) Input/Output With Schmitt Trigger
        18. 6.11.22.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        19. 6.11.22.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        20. 6.11.22.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  デバイスの項目表記
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.2 Signal Descriptions

Table 4-1 describes the device signals.

Table 4-1 Signal Descriptions – MSP430FR687x and MSP430FR687x1

TERMINAL DESCRIPTION
NAME PZ PN
NO. Seg. NO. Seg.
P4.3/UCA0SOMI/UCA0RXD/ UCB1STE 1 1 General-purpose digital I/O

USCI_A0: Slave out, master in (SPI mode)

USCI_A0: Receive data (UART mode)

USCI_B1: Slave transmit enable (SPI mode)
P1.4/UCB0CLK/UCA0STE/ TA1.0/Sx 2 S1 2 S3 General-purpose digital I/O

USCI_B0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

USCI_A0: Slave transmit enable (SPI mode)

Timer_A TA1 CCR0 capture: CCI0A input, compare: Out0 output

LCD segment output (segment number is package specific)
P1.5/UCB0STE/ UCA0CLK/TA0.0/Sx 3 S0 3 S2 General-purpose digital I/O

USCI_B0: Slave transmit enable (SPI mode)

USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

Timer_A TA0 CCR0 capture: CCI0A input, compare: Out0 output

LCD segment output (segment number is package specific)
P1.6/UCB0SIMO/UCB0SDA/ TA0.1/Sx 4 4 S1 General-purpose digital I/O

USCI_B0: Slave in, master out (SPI mode)

USCI_B0: I2C data (I2C mode)

BSL data (I2C BSL)

Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output

LCD segment output (segment number is package specific)
P1.7/UCB0SOMI/UCB0SCL/ TA0.2/Sx 5 5 S0 General-purpose digital I/O

USCI_B0: Slave out, master in (SPI mode)

USCI_B0: I2C clock (I2C mode)

BSL clock (I2C BSL)

Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output

LCD segment output (segment number is package specific)
R33/LCDCAP 6 6 Input/output port of most positive analog LCD voltage (V1)

LCD capacitor connection
P6.0/R23 7 7 General-purpose digital I/O

Input/output port of second most positive analog LCD voltage (V2)
P6.1/R13/LCDREF 8 8 General-purpose digital I/O

Input/output port of third most positive analog LCD voltage (V3 or V4)

External reference voltage input for regulated LCD voltage
P6.2/COUT/R03 9 9 General-purpose digital I/O

Comparator output

Input/output port of lowest analog LCD voltage (V5)
P6.3/COM0 10 10 General-purpose digital I/O

LCD common output COM0 for LCD backplane
P6.4/TB0.0/COM1/Sx 11 11 S36 General-purpose digital I/O

Timer_B TB0 CCR0 capture: CCI0B input, compare: Out0 output

LCD common output COM1 for LCD backplane

LCD segment output (segment number is package specific)
P6.5/TB0.1/COM2/Sx 12 12 S35 General-purpose digital I/O

Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output

LCD common output COM2 for LCD backplane

LCD segment output (segment number is package specific)
P6.6/TB0.2/COM3/Sx 13 13 S34 General-purpose digital I/O

Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output

LCD common output COM3 for LCD backplane

LCD segment output (segment number is package specific)
P2.4/TB0.3/COM4/Sx 14 S43 14 S33 General-purpose digital I/O

Timer_B TB0 CCR3 capture: CCI3A input, compare: Out3 output

LCD common output COM4 for LCD backplane

LCD segment output (segment number is package specific)
P2.5/TB0.4/COM5/Sx 15 S42 15 S32 General-purpose digital I/O

Timer_B TB0 CCR4 capture: CCI4A input, compare: Out4 output

LCD common output COM5 for LCD backplane

LCD segment output (segment number is package specific)
P2.6/TB0.5/COM6/Sx 16 S41 16 S31 General-purpose digital I/O

Timer_B TB0 CCR5 capture: CCI5A input, compare: Out5 output

LCD common output COM6 for LCD backplane

LCD segment output (segment number is package specific)
P2.7/TB0.6/COM7/Sx 17 S40 17 S30 General-purpose digital I/O

Timer_B TB0 CCR6 capture: CCI6A input, compare: Out6 output

LCD common output COM7 for LCD backplane

LCD segment output (segment number is package specific)
P10.2/TA1.0/SMCLK/Sx 18 S39 General-purpose digital I/O

Timer_A TA1 CCR0 capture: CCI0B input, compare: Out0 output

SMCLK output

LCD segment output (segment number is package specific)
P5.0/TA1.1/MCLK/Sx 19 S38 General-purpose digital I/O

Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output

MCLK output

LCD segment output (segment number is package specific)
P5.1/TA1.2/Sx 20 S37 General-purpose digital I/O

Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output

LCD segment output (segment number is package specific)
P5.2/TA1.0/TA1CLK/ACLK/Sx 21 S36 General-purpose digital I/O

Timer_A TA1 CCR0 capture: CCI0B input, compare: Out0 output

Timer_A TA1 clock signal TA0CLK input

ACLK output

LCD segment output (segment number is package specific)
P5.3/UCB1STE/Sx 22 S35 General-purpose digital I/O

USCI_B1: Slave transmit enable (SPI mode)

LCD segment output (segment number is package specific)
P3.0/UCB1CLK/Sx 23 S34 18 S29 General-purpose digital I/O

USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

LCD segment output (segment number is package specific)
P3.1/UCB1SIMO/UCB1SDA/ Sx 24 S33 19 S28 General-purpose digital I/O

USCI_B1: Slave in, master out (SPI mode)

USCI_B1: I2C data (I2C mode)

LCD segment output (segment number is package specific)
P3.2/UCB1SOMI/UCB1SCL/ Sx 25 S32 20 S27 General-purpose digital I/O

USCI_B1: Slave out, master in (SPI mode)

USCI_B1: I2C clock (I2C mode)

LCD segment output (segment number is package specific)
DVSS1 26 21 Digital ground supply
DVCC1 27 22 Digital power supply
TEST/SBWTCK 28 23 Test mode pin - select digital I/O on JTAG pins

Spy-Bi-Wire input clock
RST/NMI/SBWTDIO 29 24 Reset input, active low

Nonmaskable interrupt input

Spy-Bi-Wire data input/output
PJ.0/TDO/TB0OUTH/ SMCLK/SRSCG1 30 25 General-purpose digital I/O

Test data output port

Switch all PWM outputs high impedance input - Timer_B TB0

SMCLK output

Low-power debug: CPU Status register SCG1
PJ.1/TDI/TCLK/MCLK/ SRSCG0 31 26 General-purpose digital I/O

Test data input or test clock input

MCLK output

Low-power debug: CPU Status register SCG0
PJ.2/TMS/ACLK/SROSCOFF 32 27 General-purpose digital I/O

Test mode select

ACLK output

Low-power debug: CPU Status register OSCOFF
PJ.3/TCK/COUT/SRCPUOFF 33 28 General-purpose digital I/O

Test clock

Comparator output

Low-power debug: CPU Status register CPUOFF
P6.7/TA0CLK/Sx 34 S31 29 S26 General-purpose digital I/O

Timer_A TA0 clock signal TA0CLK input

LCD segment output (segment number is package specific)
P7.5/TA0.2/Sx 35 S30 30 S25 General-purpose digital I/O

Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output

LCD segment output (segment number is package specific)
P7.6/TA0.1/Sx 36 S29 31 S24 General-purpose digital I/O

Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output

LCD segment output (segment number is package specific)
P10.1/TA0.0/Sx 37 S28 General-purpose digital I/O

Timer_A TA0 CCR0 capture: CCI0B input, compare: Out0 output

LCD segment output (segment number is package specific)
P7.7/TA1.2/TB0OUTH/Sx 38 S27 32 S23 General-purpose digital I/O

Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output

Switch all PWM outputs high impedance input - Timer_B TB0

LCD segment output (segment number is package specific)
P3.3/TA1.1/TB0CLK/Sx 39 S26 33 S22 General-purpose digital I/O

Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output

Timer_B TB0 clock signal TB0CLK input

LCD segment output (segment number is package specific)
P3.4/UCA1SIMO/UCA1TXD/ TB0.0/Sx 40 S25 34 S21 General-purpose digital I/O

USCI_A1: Slave in, master out (SPI mode)

USCI_A1: Transmit data (UART mode)

Timer_B TB0 CCR0 capture: CCI0A input, compare: Out0 output

LCD segment output (segment number is package specific)
P3.5/UCA1SOMI/UCA1RXD/ TB0.1/Sx 41 S24 35 S20 General-purpose digital I/O

USCI_A1: Slave out, master in (SPI mode)

USCI_A1: Receive data (UART mode)

Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output

LCD segment output (segment number is package specific)
P3.6/UCA1CLK/TB0.2/Sx 42 S23 36 S19 General-purpose digital I/O

USCI_A1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output

LCD segment output (segment number is package specific)
P3.7/UCA1STE/TB0.3/Sx 43 S22 37 S18 General-purpose digital I/O

USCI_A1: Slave transmit enable (SPI mode)

Timer_B TB0 CCR3 capture: CCI3B input, compare: Out3 output

LCD segment output (segment number is package specific)
P8.0/RTCCLK/Sx 44 S21 General-purpose digital I/O

RTC clock output for calibration

LCD segment output (segment number is package specific)
P8.1/DMAE0/Sx 45 S20 General-purpose digital I/O

DMA external trigger input

LCD segment output (segment number is package specific)
P8.2/Sx 46 S19 General-purpose digital I/O

LCD segment output (segment number is package specific)
P8.3/MCLK/Sx 47 S18 General-purpose digital I/O

MCLK output

LCD segment output (segment number is package specific)
P2.3/UCA0STE/TB0OUTH/Sx 48 38 S17 General-purpose digital I/O

USCI_A0: Slave transmit enable (SPI mode)

Switch all PWM outputs high impedance input - Timer_B TB0

LCD segment output (segment number is package specific)
P2.2/UCA0CLK/TB0.4/ RTCCLK/Sx 49 39 S16 General-purpose digital I/O

USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

Timer_B TB0 CCR4 capture: CCI4B input, compare: Out4 output

RTC clock output for calibration

LCD segment output (segment number is package specific)
P2.1/UCA0SOMI/UCA0RXD/ TB0.5/DMAE0/Sx 50 40 S15 General-purpose digital I/O

USCI_A0: Slave out, master in (SPI mode)

USCI_A0: Receive data (UART mode)

BSL receive (UART BSL)

Timer_B TB0 CCR5 capture: CCI5B input, compare: Out5 output

DMA external trigger input

LCD segment output (segment number is package specific)
P2.0/UCA0SIMO/UCA0TXD/ TB0.6/TB0CLK/Sx 51 41 S14 General-purpose digital I/O

USCI_A0: Slave in, master out (SPI mode)

USCI_A0: Transmit data (UART mode)

BSL transmit (UART BSL)

Timer_B TB0 CCR6 capture: CCI6B input, compare: Out6 output

Timer_B TB0 clock signal TB0CLK input

LCD segment output (segment number is package specific)
P7.0/TA0CLK/Sx 52 S17 42 S13 General-purpose digital I/O

Timer_A TA0 clock signal TA0CLK input

LCD segment output (segment number is package specific)
P7.1/TA0.0/ACLK/Sx 53 S16 43 S12 General-purpose digital I/O

Timer_A TA0 CCR0 capture: CCI0B input, compare: Out0 output

ACLK output

LCD segment output (segment number is package specific)
P7.2/TA0.1/Sx 54 S15 44 S11 General-purpose digital I/O

Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output

LCD segment output (segment number is package specific)
P7.3/TA0.2/Sx 55 S14 45 S10 General-purpose digital I/O

Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output

LCD segment output (segment number is package specific)
P7.4/SMCLK/Sx 56 S13 General-purpose digital I/O

SMCLK output

LCD segment output (segment number is package specific)
DVSS2 57 46 Digital ground supply
DVCC2 58 47 Digital power supply
P8.4/A7/C7 59 General-purpose digital I/O

Analog input A7

Comparator input C7
P8.5/A6/C6 60 General-purpose digital I/O

Analog input A6

Comparator input C6
P8.6/A5/C5 61 General-purpose digital I/O

Analog input A5

Comparator input C5
P8.7/A4/C4 62 General-purpose digital I/O

Analog input A4

Comparator input C4
P1.3/TA1.2/A3/C3 63 48 General-purpose digital I/O

Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output

Analog input A3

Comparator input C3
P1.2/TA1.1/TA0CLK/ COUT/A2/C2 64 49 General-purpose digital I/O

Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output

Timer_A TA0 clock signal TA0CLK input

Comparator output

Analog input A2

Comparator input C2
P1.1/TA0.2/TA1CLK/ COUT/A1/C1/VREF+/VeREF+ 65 50 General-purpose digital I/O

Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output

Timer_A TA1 clock signal TA1CLK input

Comparator output

Analog input A1

Comparator input C1

Output of positive reference voltage

Input for an external positive reference voltage to the ADC
P1.0/TA0.1/DMAE0/ RTCCLK/A0/C0/ VREF-/VeREF- 66 51 General-purpose digital I/O

Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output

DMA external trigger input

RTC clock output for calibration

Analog input A0

Comparator input C0

Output of negative reference voltage

Input for an external negative reference voltage to the ADC
P9.0/A8/C8 67 52 General-purpose digital I/O

Analog input A8

Comparator input C8
P9.1/A9/C9 68 53 General-purpose digital I/O

Analog input A9

Comparator input C9
P9.2/A10/C10 69 54 General-purpose digital I/O

Analog input A10; comparator input C10
P9.3/A11/C11 70 55 General-purpose digital I/O

Analog input A11

Comparator input C11
P9.4/A12/C12 71 56 General-purpose digital I/O

Analog input A12

Comparator input C12
P9.5/A13/C13 72 57 General-purpose digital I/O

Analog input A13

Comparator input C13
P9.6/A14/C14 73 58 General-purpose digital I/O

Analog input A14

Comparator input C14
P9.7/A15/C15 74 59 General-purpose digital I/O

Analog input A15

Comparator input C15
DVCC4 75 60 Digital power supply
DVSS4 76 61 Digital ground supply
NC 77 62 No connect
NC 78 63 No connect
AVCC1 79 64 Analog power supply
AVSS3 80 65 Analog ground supply
PJ.7/HFXOUT 81 66 General-purpose digital I/O

Output terminal of crystal oscillator XT2
PJ.6/HFXIN 82 67 General-purpose digital I/O

Input terminal for crystal oscillator XT2
AVSS1 83 68 Analog ground supply
PJ.4/LFXIN 84 69 General-purpose digital I/O

Input terminal for crystal oscillator XT1
PJ.5/LFXOUT 85 70 General-purpose digital I/O

Output terminal of crystal oscillator XT1
AVSS2 86 71 Analog ground supply
P5.4/UCA1SIMO/UCA1TXD/Sx 87 S12 General-purpose digital I/O

USCI_A1: Slave in, master out (SPI mode)

USCI_A1: Transmit data (UART mode)

LCD segment output (segment number is package specific)
P5.5/UCA1SOMI/UCA1RXD/ Sx 88 S11 General-purpose digital I/O

USCI_A1: Slave out, master in (SPI mode)

USCI_A1: Receive data (UART mode)

LCD segment output (segment number is package specific)
P5.6/UCA1CLK/Sx 89 S10 General-purpose digital I/O

USCI_A1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

LCD segment output (segment number is package specific)
P5.7/UCA1STE/TB0CLK/Sx 90 S9 General-purpose digital I/O

USCI_A1: Slave transmit enable (SPI mode)

Timer_B TB0 clock signal TB0CLK input

LCD segment output (segment number is package specific)
P4.4/UCB1STE/TA1CLK/Sx 91 S8 72 S9 General-purpose digital I/O

USCI_B1: Slave transmit enable (SPI mode)

Timer_A TA1 clock signal TA1CLK input

LCD segment output (segment number is package specific)
P4.5/UCB1CLK/TA1.0/Sx 92 S7 73 S8 General-purpose digital I/O

USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

Timer_A TA1 CCR0 capture: CCI0A input, compare: Out0 output

LCD segment output (segment number is package specific)
P4.6/UCB1SIMO/UCB1SDA/ TA1.1/Sx 93 S6 74 S7 General-purpose digital I/O

USCI_B1: Slave in, master out (SPI mode)

USCI_B1: I2C data (I2C mode)

Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output

LCD segment output (segment number is package specific)
P4.7/UCB1SOMI/UCB1SCL/ TA1.2/Sx 94 S5 75 S6 General-purpose digital I/O

USCI_B1: Slave out, master in (SPI mode)

USCI_B1: I2C clock (I2C mode)

Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output

LCD segment output (segment number is package specific)
P10.0/SMCLK/Sx 95 S4 General-purpose digital I/O

SMCLK output

LCD segment output (segment number is package specific)
P4.0/UCB1SIMO/UCB1SDA/ MCLK/Sx 96 S3 76 S5 General-purpose digital I/O

USCI_B1: Slave in, master out (SPI mode)

USCI_B1: I2C data (I2C mode)

MCLK output

LCD segment output (segment number is package specific)
P4.1/UCB1SOMI/UCB1SCL/ ACLK/Sx 97 S2 77 S4 General-purpose digital I/O

USCI_B1: Slave out, master in (SPI mode)

USCI_B1: I2C clock (I2C mode)

ACLK output

LCD segment output (segment number is package specific)
DVSS3 98 78 Digital ground supply
DVCC3 99 79 Digital power supply
P4.2/UCA0SIMO/UCA0TXD/ UCB1CLK 100 80 General-purpose digital I/O

USCI_A0: Slave in, master out (SPI mode)

USCI_A0: Transmit data (UART mode)

USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)