JAJSG20C August 2014 – August 2018 MSP430FR6877 , MSP430FR6879 , MSP430FR68791
PRODUCTION DATA.
The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to 0FF80h. Figure 6-1 summarizes the content of this address range.
The power-up start address or reset vector is located at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-4 shows the device-specific interrupt vector locations.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as the BSL password (if enabled by the corresponding signature).
The signatures are located at 0FF80h and extend to higher addresses. Signatures are evaluated during device start-up. Table 6-5 shows the device-specific signature locations.
A JTAG password can be programmed starting at address 0FF88h and extending to higher addresses. The password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for the password. The length of the JTAG password depends on the JTAG signature.
See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide for details.
INTERRUPT SOURCE | INTERRUPT FLAG | SYSTEM INTERRUPT | WORD ADDRESS | PRIORITY |
---|---|---|---|---|
System Reset
Power up, Brownout, Supply Supervisor External Reset RST Watchdog time-out (watchdog mode) WDT, FRCTL MPU, CS, PMM password violation FRAM uncorrectable bit error detection MPU segment violation FRAM access time error Software POR, BOR |
SVSHIFG PMMRSTIFG WDTIFG WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW UBDIFG MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG ACCTEIFG PMMPORIFG, PMMBORIFG (SYSRSTIV) (1)(2) |
Reset | 0FFFEh | Highest |
System NMI
Vacant memory access JTAG mailbox FRAM bit error detection MPU segment violation |
VMAIFG JMBINIFG, JMBOUTIFG CBDIFG, UBDIFG MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG (SYSSNIV) (1)(3) |
(Non)maskable | 0FFFCh | |
User NMI
External NMI Oscillator fault |
NMIIFG, OFIFG
(SYSUNIV) (1)(3) |
(Non)maskable | 0FFFAh | |
Comparator_E | Comparator_E interrupt flags
(CEIV) (1) |
Maskable | 0FFF8h | |
Timer_B TB0 | TB0CCR0.CCIFG | Maskable | 0FFF6h | |
Timer_B TB0 | TB0CCR1.CCIFG to TB0CCR6.CCIFG,
TB0CTL.TBIFG (TB0IV)(1) |
Maskable | 0FFF4h | |
Watchdog timer
(interval timer mode) |
WDTIFG | Maskable | 0FFF2h | |
eUSCI_A0 receive or transmit | UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) (UCA0IV)(1) |
Maskable | 0FFEEh | |
eUSCI_B0 receive or transmit | UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode) (UCB0IV)(1) |
Maskable | 0FFECh | |
ADC12_B | ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG, ADC12RDYIFG, ADC12OVIFG, ADC12TOVIFG (ADC12IV) (1) |
Maskable | 0FFEAh | |
Timer_A TA0 | TA0CCR0.CCIFG | Maskable | 0FFE8h | |
Timer_A TA0 | TA0CCR1.CCIFG to TA0CCR2.CCIFG,
TA0CTL.TAIFG (TA0IV)(1) |
Maskable | 0FFE6h | |
eUSCI_A1 receive or transmit | UCA1IFG:UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) (UCA1IV)(1) |
Maskable | 0FFE4h | |
eUSCI_B1 receive or transmit) | UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode) (UCB1IV)(1) |
Maskable | 0FFE2h | |
DMA | DMA0CTL.DMAIFG, DMA1CTL.DMAIFG, DMA2CTL.DMAIFG
(DMAIV)(1) |
Maskable | 0FFE0h | |
Timer_A TA1 | TA1CCR0.CCIFG | Maskable | 0FFDEh | |
Timer_A TA1 | TA1CCR1.CCIFG to TA1CCR2.CCIFG,
TA1CTL.TAIFG (TA1IV)(1) |
Maskable | 0FFDCh | |
I/O Port P1 | P1IFG.0 to P1IFG.7
(P1IV)(1) |
Maskable | 0FFDAh | |
Timer_A TA2 | TA2CCR0.CCIFG | Maskable | 0FFD8h | |
Timer_A TA2 | TA2CCR1.CCIFG
TA2CTL.TAIFG (TA2IV)(1) |
Maskable | 0FFD6h | |
I/O Port P2 | P2IFG.0 to P2IFG.7
(P2IV) (1) |
Maskable | 0FFD4h | |
Timer_A TA3 | TA3CCR0.CCIFG | Maskable | 0FFD2h | |
Timer_A TA3 | TA3CCR1.CCIFG
TA3CTL.TAIFG (TA3IV)(1) |
Maskable | 0FFD0h | |
I/O Port P3 | P3IFG.0 to P3IFG.7
(P3IV) (1) |
Maskable | 0FFCEh | |
I/O Port P4 | P4IFG.0 to P4IFG.7
(P4IV) (1) |
Maskable | 0FFCCh | |
LCD_C | LCD_C interrupt flags (LCDCIV) (1) | Maskable | 0FFCAh | |
RTC_C | RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG
(RTCIV) (1) |
Maskable | 0FFC8h | Lowest |
SIGNATURE | WORD ADDRESS |
---|---|
IP Encapsulation Signature2 | 0FF8Ah |
IP Encapsulation Signature1 (1) | 0FF88h |
BSL Signature2 | 0FF86h |
BSL Signature1 | 0FF84h |
JTAG Signature2 | 0FF82h |
JTAG Signature1 | 0FF80h |