JAJSG18C August 2014 – August 2018 MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tSTE,LEAD | STE lead time, STE active to clock | UCSTEM = 1,
UCMODEx = 01 or 10 |
1 | UCxCLK cycles | |||
tSTE,LAG | STE lag time, last clock to STE inactive | UCSTEM = 1,
UCMODEx = 01 or 10 |
1 | UCxCLK cycles | |||
tSTE,ACC | STE access time, STE active to SIMO data out | UCSTEM = 0,
UCMODEx = 01 or 10 |
2.2 V, 3.0 V | 60 | ns | ||
tSTE,DIS | STE disable time, STE inactive to SOMI high impedance | UCSTEM = 0,
UCMODEx = 01 or 10 |
2.2 V, 3.0 V | 80 | ns | ||
tSU,MI | SOMI input data setup time | 2.2 V | 40 | ns | |||
3.0 V | 40 | ||||||
tHD,MI | SOMI input data hold time | 2.2 V | 0 | ns | |||
3.0 V | 0 | ||||||
tVALID,MO | SIMO output data valid time(2) | UCLK edge to SIMO valid,
CL = 20 pF |
2.2 V | 10 | ns | ||
3.0 V | 10 | ||||||
tHD,MO | SIMO output data hold time(3) | CL = 20 pF | 2.2 V | 0 | ns | ||
3.0 V | 0 |
Table 5-20 lists the characteristics of the eUSCI in SPI slave mode.