JAJSG17 データシート

JAJSG17D June 2014 – August 2018 MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR59891 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PN|80
- MTQF010B
PZ|100
- MTQF013A

サーマルパッド・メカニカル・データ

PZ|100
- QFND428

発注情報

3 Device Comparison

Table 3-1 and Table 3-2 summarize the available family members.

Table 3-1 Device Comparison (With UART BSL)⁽¹⁾⁽²⁾

DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	Timer_A ⁽³⁾	Timer_B ⁽⁴⁾	eUSCI		AES	ADC12_B	LCD_C	I/O	PACKAGE
DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	Timer_A ⁽³⁾	Timer_B ⁽⁴⁾	A⁽⁷⁾	B⁽⁸⁾	AES	ADC12_B	LCD_C	I/O	PACKAGE
MSP430FR6989	128	2	DCO HFXT LFXT	3, 3 ⁽⁵⁾ 2, 5 ⁽⁶⁾	7	2	2	yes	12 ext 16 ext	240 seg 320 seg	63 83	80 PN 100 PZ
MSP430FR6988	96	2	DCO HFXT LFXT	3, 3 ⁽⁵⁾ 2, 5 ⁽⁶⁾	7	2	2	yes	12 ext 16 ext	240 seg 320 seg	63 83	80 PN 100 PZ
MSP430FR6987	64	2	DCO HFXT LFXT	3, 3 ⁽⁵⁾ 2, 5 ⁽⁶⁾	7	2	2	yes	12 ext 16 ext	240 seg 320 seg	63 83	80 PN 100 PZ
MSP430FR5989	128	2	DCO HFXT LFXT	3, 3 ⁽⁵⁾ 2, 5 ⁽⁶⁾	7	2	2	yes	12 ext	N/A	48	64 PM 64 RGC
MSP430FR5988	96	2	DCO HFXT LFXT	3, 3 ⁽⁵⁾ 2, 5 ⁽⁶⁾	7	2	2	yes	12 ext	N/A	48	64 PM 64 RGC
MSP430FR5987	64	2	DCO HFXT LFXT	3, 3 ⁽⁵⁾ 2, 5 ⁽⁶⁾	7	2	2	yes	12 ext	N/A	48	64 PM 64 RGC
MSP430FR5986	48	2	DCO HFXT LFXT	3, 3 ⁽⁵⁾ 2, 5 ⁽⁶⁾	7	2	2	yes	12 ext	N/A	48	64 PM

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/package.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(5) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.

(6) Timer_A TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).

(7) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.

(8) eUSCI_B supports I²C with multiple slave addresses and SPI.

Table 3-2 Device Comparison (With I²C BSL) ⁽¹⁾⁽²⁾

DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	Timer_A ⁽³⁾	Timer_B ⁽⁴⁾	eUSCI		AES	ADC12_B	LCD_C	I/O	PACKAGE TYPE
DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	Timer_A ⁽³⁾	Timer_B ⁽⁴⁾	A⁽⁷⁾	B⁽⁸⁾	AES	ADC12_B	LCD_C	I/O	PACKAGE TYPE
MSP430FR69891	128	2	DCO HFXT LFXT	3, 3 ⁽⁵⁾ 2, 5 ⁽⁶⁾	7	2	2	yes	12 ext 16 ext	240 seg 320 seg	63 83	80 PN 100 PZ
MSP430FR59891	128	2	DCO HFXT LFXT	3, 3 ⁽⁵⁾ 2, 5 ⁽⁶⁾	7	2	2	yes	12 ext	N/A	48	64 PM 64 RGC