SLAS892C March   2013  – September 2014 MSP430G2444 , MSP430G2544 , MSP430G2744

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Handling Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current (Into DVCC + AVCC) Excluding External Current
    5. 5.5  Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC)
    6. 5.6  Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current
    7. 5.7  Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)
    8. 5.8  Leakage Current, Ports Px
    9. 5.9  Outputs, Ports Px
    10. 5.10 Output Frequency, Ports Px
    11. 5.11 Typical Characteristics - Outputs
    12. 5.12 POR and BOR
    13. 5.13 Typical Characteristics - POR and BOR
    14. 5.14 DCO Frequency
    15. 5.15 Calibrated DCO Frequencies, Tolerance
    16. 5.16 Wake-Up From Lower-Power Modes (LPM3, LPM4)
    17. 5.17 Typical Characteristics - DCO Clock Wake-Up Time From LPM3 or LPM4
    18. 5.18 DCO With External Resistor ROSC
    19. 5.19 Typical Characteristics - DCO With External Resistor ROSC
    20. 5.20 Crystal Oscillator LFXT1, Low-Frequency Mode
    21. 5.21 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    22. 5.22 Crystal Oscillator LFXT1, High-Frequency Mode
    23. 5.23 Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
    24. 5.24 Timer_A, Timer_B
    25. 5.25 USCI (UART Mode)
    26. 5.26 USCI (SPI Master Mode)
    27. 5.27 USCI (SPI Slave Mode)
    28. 5.28 USCI (I2C Mode)
    29. 5.29 10-Bit ADC, Power Supply and Input Range Conditions
    30. 5.30 10-Bit ADC, Built-In Voltage Reference
    31. 5.31 10-Bit ADC, External Reference
    32. 5.32 10-Bit ADC, Timing Parameters
    33. 5.33 10-Bit ADC, Linearity Parameters
    34. 5.34 10-Bit ADC, Temperature Sensor and Built-In VMID
    35. 5.35 Flash Memory
    36. 5.36 RAM
    37. 5.37 JTAG and Spy-Bi-Wire Interface
    38. 5.38 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers
      1. 6.5.1 Interrupt Enable 1
      2. 6.5.2 Interrupt Enable 2
      3. 6.5.3 Interrupt Flag Register 1
      4. 6.5.4 Interrupt Flag Register 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
    10. 6.10 Oscillator and System Clock
    11. 6.11 Brownout
    12. 6.12 Digital I/O
    13. 6.13 Watchdog Timer (WDT+)
    14. 6.14 Timer_A3
    15. 6.15 Timer_B3
    16. 6.16 Universal Serial Communications Interface (USCI)
    17. 6.17 ADC10
    18. 6.18 Peripheral File Map
    19. 6.19 Port Schematics
      1. 6.19.1  Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
      2. 6.19.2  Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access Features
      3. 6.19.3  Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features
      4. 6.19.4  Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger
      5. 6.19.5  Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger
      6. 6.19.6  Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger
      7. 6.19.7  Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger
      8. 6.19.8  Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
      9. 6.19.9  Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input
      10. 6.19.10 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output
      11. 6.19.11 Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger
      12. 6.19.12 Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger
      13. 6.19.13 Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger
      14. 6.19.14 Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger
      15. 6.19.15 Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger
      16. 6.19.16 Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger
      17. 6.19.17 Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger
      18. 6.19.18 Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger
      19. 6.19.19 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Target Socket Boards
          2. 7.1.2.2.2 Experimenter Boards
          3. 7.1.2.2.3 Debugging and Programming Tools
          4. 7.1.2.2.4 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 Command-Line Programmer
      3. 7.1.3 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Related Links
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pin diagram for the 38-pin DA package.

po_da38_22x2_slas892.gifFigure 4-1 38-Pin TSSOP (DA Package) (Top View)

Figure 4-2 shows the pin diagram for the 40-pin N package.

po_n40_22x2_slas892.gifFigure 4-2 40-Pin PDIP (N Package) (Top View)

Figure 4-3 shows the pin diagram for the 40-pin RHA package.

po_rha40_22x2_slas892.gifFigure 4-3 40-Pin QFN (RHA Package) (Top View)

Figure 4-4 shows the pin diagram for the 49-pin YFF package.

po_yff49_slas892.gifFigure 4-4 49-Pin DSBGA (YFF Package)

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Terminal Functions

TERMINAL I/O DESCRIPTION
NAME NO.
YFF DA N RHA
P1.0/TACLK/ADC10CLK F2 31 33 29 I/O General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ADC10, conversion clock
P1.1/TA0 G2 32 34 30 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: OUT0 output; BSL transmit
P1.2/TA1 E2 33 35 31 I/O General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
P1.3/TA2 G1 34 36 32 I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
P1.4/SMCLK/TCK F1 35 37 33 I/O General-purpose digital I/O pin
SMCLK signal output
Test Clock input for device programming and test
P1.5/TA0/TMS E1 36 38 34 I/O General-purpose digital I/O pin
Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
P1.6/TA1/TDI/TCLK E3 37 39 35 I/O General-purpose digital I/O pin
Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
P1.7/TA2/TDO/TDI(1) D2 38 40 36 I/O General-purpose digital I/O pin
Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
P2.0/ACLK/A0 A4 8 10 6 I/O General-purpose digital I/O pin
ACLK output
ADC10, analog input A0
P2.1/TAINCLK/ SMCLK/A1 B4 9 11 7 I/O General-purpose digital I/O pin
Timer_A, clock signal at INCLK, SMCLK signal output
ADC10, analog input A1
P2.2/TA0/A2 A5 10 12 8 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0B input; BSL receive, compare: OUT0 output
ADC10, analog input A2
P2.3/TA1/A3/ VREF-/VeREF- F3 29 31 27 I/O General-purpose digital I/O pin
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3
Negative reference voltage output/input
P2.4/TA2/A4/ VREF+/VeREF+ G3 30 32 28 I/O General-purpose digital I/O pin
Timer_A, compare: OUT2 output
ADC10, analog input A4
Positive reference voltage output/input
P2.5/ROSC C2 3 4 40 I/O General-purpose digital I/O pin
Input for external DCO resistor to define DCO frequency
XIN/P2.6 A2 6 7 3 I/O Input terminal of crystal oscillator
General-purpose digital I/O pin
XOUT/P2.7 A1 5 6 2 I/O Output terminal of crystal oscillator
General-purpose digital I/O pin(2)
P3.0/UCB0STE/ UCA0CLK/A5 B5 11 13 9 I/O General-purpose digital I/O pin
USCI_B0 slave transmit enable
USCI_A0 clock input/output
ADC10, analog input A5
P3.1/UCB0SIMO/ UCB0SDA A6 12 14 10 I/O General-purpose digital I/O pin
USCI_B0 slave in, master out in SPI mode
USCI_B0 SDA I2C data in I2C mode
P3.2/UCB0SOMI/ UCB0SCL A7 13 15 11 I/O General-purpose digital I/O pin
USCI_B0 slave out, master in SPI mode
USCI_B0 SCL I2C clock in I2C mode
P3.3/UCB0CLK/ UCA0STE B6 14 16 12 I/O General-purpose digital I/O pin
USCI_B0 clock input/output
USCI_A0 slave transmit enable
P3.4/UCA0TXD/ UCA0SIMO G6 25 27 23 I/O General-purpose digital I/O pin
USCI_A0 transmit data output in UART mode
USCI_A0 slave in, master out in SPI mode
P3.5/UCA0RXD/ UCA0SOMI G5 26 28 24 I/O General-purpose digital I/O pin
USCI_A0 receive data input in UART mode
USCI_A0 slave out, master in SPI mode
P3.6/A6 F4 27 29 25 I/O General-purpose digital I/O pin
ADC10 analog input A6
P3.7/A7 G4 28 30 26 I/O General-purpose digital I/O pin
ADC10 analog input A7
P4.0/TB0 D6 17 19 15 I/O General-purpose digital I/O pin
Timer_B, capture: CCI0A input, compare: OUT0 output
P4.1/TB1 D7 18 20 16 I/O General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
P4.2/TB2 E6 19 21 17 I/O General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
P4.3/TB0/A12 E7 20 22 18 I/O General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
P4.4/TB1/A13 F7 21 23 19 I/O General-purpose digital I/O pin
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
P4.5/TB2/A14 F6 22 24 20 I/O General-purpose digital I/O pin
Timer_B, compare: OUT2 output
ADC10 analog input A14
P4.6/TBOUTH/A15 G7 23 25 21 I/O General-purpose digital I/O pin
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
P4.7/TBCLK F5 24 26 22 I/O General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
RST/NMI/SBWTDIO B3 7 9 5 I Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/SBWTCK D1 1 1 37 I Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC C1, D3, D4, E4, E5 2 2, 3 38, 39 Digital supply voltage
AVCC C6, C7, D5 16 18 14 Analog supply voltage
DVSS A3, B1, B2, C3, C4 4 5, 8 1, 4 Digital ground reference
AVSS B7, C5 15 17 13 Analog ground reference
QFN Pad NA NA NA Pad NA QFN package pad; connection to DVSS recommended.
(1) TDO or TDI is selected via JTAG instruction.
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset.