SLAS892C March   2013  – September 2014 MSP430G2444 , MSP430G2544 , MSP430G2744

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Handling Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current (Into DVCC + AVCC) Excluding External Current
    5. 5.5  Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC)
    6. 5.6  Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current
    7. 5.7  Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)
    8. 5.8  Leakage Current, Ports Px
    9. 5.9  Outputs, Ports Px
    10. 5.10 Output Frequency, Ports Px
    11. 5.11 Typical Characteristics - Outputs
    12. 5.12 POR and BOR
    13. 5.13 Typical Characteristics - POR and BOR
    14. 5.14 DCO Frequency
    15. 5.15 Calibrated DCO Frequencies, Tolerance
    16. 5.16 Wake-Up From Lower-Power Modes (LPM3, LPM4)
    17. 5.17 Typical Characteristics - DCO Clock Wake-Up Time From LPM3 or LPM4
    18. 5.18 DCO With External Resistor ROSC
    19. 5.19 Typical Characteristics - DCO With External Resistor ROSC
    20. 5.20 Crystal Oscillator LFXT1, Low-Frequency Mode
    21. 5.21 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    22. 5.22 Crystal Oscillator LFXT1, High-Frequency Mode
    23. 5.23 Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
    24. 5.24 Timer_A, Timer_B
    25. 5.25 USCI (UART Mode)
    26. 5.26 USCI (SPI Master Mode)
    27. 5.27 USCI (SPI Slave Mode)
    28. 5.28 USCI (I2C Mode)
    29. 5.29 10-Bit ADC, Power Supply and Input Range Conditions
    30. 5.30 10-Bit ADC, Built-In Voltage Reference
    31. 5.31 10-Bit ADC, External Reference
    32. 5.32 10-Bit ADC, Timing Parameters
    33. 5.33 10-Bit ADC, Linearity Parameters
    34. 5.34 10-Bit ADC, Temperature Sensor and Built-In VMID
    35. 5.35 Flash Memory
    36. 5.36 RAM
    37. 5.37 JTAG and Spy-Bi-Wire Interface
    38. 5.38 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers
      1. 6.5.1 Interrupt Enable 1
      2. 6.5.2 Interrupt Enable 2
      3. 6.5.3 Interrupt Flag Register 1
      4. 6.5.4 Interrupt Flag Register 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
    10. 6.10 Oscillator and System Clock
    11. 6.11 Brownout
    12. 6.12 Digital I/O
    13. 6.13 Watchdog Timer (WDT+)
    14. 6.14 Timer_A3
    15. 6.15 Timer_B3
    16. 6.16 Universal Serial Communications Interface (USCI)
    17. 6.17 ADC10
    18. 6.18 Peripheral File Map
    19. 6.19 Port Schematics
      1. 6.19.1  Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
      2. 6.19.2  Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access Features
      3. 6.19.3  Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features
      4. 6.19.4  Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger
      5. 6.19.5  Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger
      6. 6.19.6  Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger
      7. 6.19.7  Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger
      8. 6.19.8  Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
      9. 6.19.9  Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input
      10. 6.19.10 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output
      11. 6.19.11 Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger
      12. 6.19.12 Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger
      13. 6.19.13 Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger
      14. 6.19.14 Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger
      15. 6.19.15 Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger
      16. 6.19.16 Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger
      17. 6.19.17 Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger
      18. 6.19.18 Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger
      19. 6.19.19 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Target Socket Boards
          2. 7.1.2.2.2 Experimenter Boards
          3. 7.1.2.2.3 Debugging and Programming Tools
          4. 7.1.2.2.4 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 Command-Line Programmer
      3. 7.1.3 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Related Links
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.