JAJSE27 October   2017 MSP432E401Y

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. Table 5-3 Power and Brownout Levels
          2. 5.15.2.1.1 VDDA Levels
          3. 5.15.2.1.2 VDD Levels
          4. 5.15.2.1.3 VDDC Levels
          5. 5.15.2.1.4 VDD Glitch Response
          6. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
        1. Table 5-4 Reset Characteristics
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. Table 5-5 Phase Locked Loop (PLL) Characteristics
          2. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
          1. Table 5-9 Low-Frequency Oscillator Characteristics
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
          1. Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics
          2. Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics
        5. 5.15.4.5 Main Oscillator Specifications
          1. Table 5-12 Main Oscillator Input Characteristics
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
          1. Table 5-14 System Clock Characteristics With ADC Operation
        7. 5.15.4.7 System Clock Characteristics With USB Operation
          1. Table 5-15 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
        1. Table 5-16 Wake From Sleep Characteristics
        2. Table 5-17 Wake From Deep Sleep Characteristics
      6. 5.15.6  Hibernation Module
        1. Table 5-18 Hibernation Module Battery Characteristics
        2. Table 5-19 Hibernation Module Characteristics
        3. Table 5-20 Hibernation Module Tamper I/O Characteristics
      7. 5.15.7  Flash Memory
        1. Table 5-21 Flash Memory Characteristics
      8. 5.15.8  EEPROM
        1. Table 5-22 EEPROM Characteristics
      9. 5.15.9  Input/Output Pin Characteristics
        1. Table 5-23 Fast GPIO Module Characteristics
        2. Table 5-24 Slow GPIO Module Characteristics
        3. 5.15.9.1    Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
            1. Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin
          2. 5.15.9.1.2 Nonpower I/O Pins
            1. Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics
      10. 5.15.10 External Peripheral Interface (EPI)
        1. Table 5-28 EPI SDRAM Characteristics
        2. Table 5-29 EPI SDRAM Interface Characteristics
        3. Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
        4. Table 5-31 EPI General-Purpose Interface Characteristics
        5. Table 5-32 EPI PSRAM Interface Characteristics
      11. 5.15.11 Analog-to-Digital Converter (ADC)
        1. Table 5-33 Electrical Characteristics for ADC at 1 Msps
        2. Table 5-34 Electrical Characteristics for ADC at 2 Msps
      12. 5.15.12 Synchronous Serial Interface (SSI)
        1. Table 5-35 SSI Characteristics
        2. Table 5-36 Bi- and Quad-SSI Characteristics
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
        1. Table 5-37 I2C Characteristics
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
          1. Table 5-38 Ethernet PHY DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
          1. Table 5-39 MOSC 25-MHz Crystal Specification
          2. Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification
        3. 5.15.14.3 AC Characteristics
          1. Table 5-41 Ethernet Controller Enable and Software Reset Timing
          2. Table 5-42 100Base-TX Transmit Timing
          3. Table 5-43 10Base-T Normal Link Pulse Timing
          4. Table 5-44 Auto-Negotiation Fast Link Pulse (FLP) Timing
          5. Table 5-45 100Base-TX Signal Detect Timing
      15. 5.15.15 Universal Serial Bus (USB) Controller
        1. Table 5-46 ULPI Interface Timing
      16. 5.15.16 Analog Comparator
        1. Table 5-47 Analog Comparator Characteristics
        2. Table 5-48 Analog Comparator Characteristics
        3. Table 5-49 Analog Comparator Voltage Reference Characteristics
        4. Table 5-50 Analog Comparator Voltage Reference Characteristics
      17. 5.15.17 Pulse-Width Modulator (PWM)
        1. Table 5-51 PWM Timing Characteristics
      18. 5.15.18 Emulation and Debug
        1. Table 5-52 JTAG Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 Inter-Integrated Circuit (I2C)
        6. 6.5.6.6 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  Advanced Motion Control
        1. 6.5.8.1 Pulse Width Modulation (PWM)
        2. 6.5.8.2 Quadrature Encoder With Index (QEI) Module
      9. 6.5.9  Analog
        1. 6.5.9.1 ADC
        2. 6.5.9.2 Analog Comparators
      10. 6.5.10 JTAG and Arm Serial Wire Debug
      11. 6.5.11 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 使い始めと次の手順
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.3 Signal Descriptions

Table 4-3 describes the signals. The signals are sorted by function.

Table 4-3 Signal Descriptions

FUNCTIONSIGNAL NAMEPIN NO.PIN TYPEDESCRIPTION
ADC AIN0 12 I

Analog-to-digital converter input 0.
AIN1 13 I Analog-to-digital converter input 1
AIN2 14 I Analog-to-digital converter input 2
AIN3 15 I Analog-to-digital converter input 3
AIN4 128 I Analog-to-digital converter input 4
AIN5 127 I Analog-to-digital converter input 5
AIN6 126 I Analog-to-digital converter input 6
AIN7 125 I Analog-to-digital converter input 7
AIN8 124 I Analog-to-digital converter input 8
AIN9 123 I Analog-to-digital converter input 9
AIN10 121 I Analog-to-digital converter input 10
AIN11 120 I Analog-to-digital converter input 11
AIN12 4 I Analog-to-digital converter input 12
AIN13 3 I Analog-to-digital converter input 13
AIN14 2 I Analog-to-digital converter input 14
AIN15 1 I Analog-to-digital converter input 15
AIN16 18 I Analog-to-digital converter input 16
AIN17 19 I Analog-to-digital converter input 17
AIN18 20 I Analog-to-digital converter input 18
AIN19 21 I Analog-to-digital converter input 19
VREFA+ 9 - A reference voltage used to specify the voltage at which the ADC converts to a maximum value. This pin is used in conjunction with GNDA. The voltage that is applied to VREFA+ is the voltage with which an AINn signal is converted to 4095. The VREFA+ voltage is limited to the range specified in the ADC electrical specifications.
Analog Comparators C0+ 23 I Analog comparator 0 positive input
C0- 22 I Analog comparator 0 negative input
C0o 1
83		 O Analog comparator 0 output
C1+ 24 I Analog comparator 1 positive input
C1- 25 I Analog comparator 1 negative input
C1o 2
84		 O Analog comparator 1 output
C2+ 118 I Analog comparator 2 positive input
C2- 119 I Analog comparator 2 negative input
C2o 3 O Analog comparator 2 output
Controller Area Network CAN0Rx 33 I CAN module 0 receive
CAN0Tx 34 O CAN module 0 transmit
CAN1Rx 95 I CAN module 1 receive
CAN1Tx 96 O CAN module 1 transmit
Core TRCLK 45 O

Trace clock.
TRD0 44 O

Trace data 0.
TRD1 43 O

Trace data 1.
TRD2 42 O

Trace data 2.
TRD3 46 O

Trace data 3.
Ethernet EN0LED0 42
63		 O Ethernet 0 LED 0
EN0LED1 46
61		 O Ethernet 0 LED 1
EN0LED2 43
62		 O Ethernet 0 LED 2
EN0PPS 49
116		 O Ethernet 0 pulse-per-second (PPS) output
EN0RXIN 53 I/O Ethernet PHY negative receive differential input
EN0RXIP 54 I/O Ethernet PHY positive receive differential input
EN0TXON 56 I/O Ethernet PHY negative transmit differential output
EN0TXOP 57 I/O Ethernet PHY positive transmit differential output
RBIAS 59 O 4.87-kΩ resistor (1% precision) for Ethernet PHY
External Peripheral Interface EPI0S0 18
29		 I/O EPI module 0 signal 0
EPI0S1 19
30		 I/O EPI module 0 signal 1
EPI0S2 20
31		 I/O EPI module 0 signal 2
EPI0S3 21
32		 I/O EPI module 0 signal 3
EPI0S4 22 I/O EPI module 0 signal 4
EPI0S5 23 I/O EPI module 0 signal 5
EPI0S6 24 I/O EPI module 0 signal 6
EPI0S7 25 I/O EPI module 0 signal 7
EPI0S8 40 I/O EPI module 0 signal 8
EPI0S9 41 I/O EPI module 0 signal 9
EPI0S10 50 I/O EPI module 0 signal 10
EPI0S11 49 I/O EPI module 0 signal 11
EPI0S12 75 I/O EPI module 0 signal 12
EPI0S13 76 I/O EPI module 0 signal 13
EPI0S14 77 I/O EPI module 0 signal 14
EPI0S15 78 I/O EPI module 0 signal 15
EPI0S16 81 I/O EPI module 0 signal 16
EPI0S17 82 I/O EPI module 0 signal 17
EPI0S18 83 I/O EPI module 0 signal 18
EPI0S19 84 I/O EPI module 0 signal 19
EPI0S20 5 I/O EPI module 0 signal 20
EPI0S21 6 I/O EPI module 0 signal 21
EPI0S22 11 I/O EPI module 0 signal 22
EPI0S23 27 I/O EPI module 0 signal 23
EPI0S24 60 I/O EPI module 0 signal 24
EPI0S25 61 I/O EPI module 0 signal 25
EPI0S26 85 I/O EPI module 0 signal 26
EPI0S27 91 I/O EPI module 0 signal 27
EPI0S28 92 I/O EPI module 0 signal 28
EPI0S29 103
109		 I/O EPI module 0 signal 29
EPI0S30 104
110		 I/O EPI module 0 signal 30
EPI0S31 62 I/O EPI module 0 signal 31
EPI0S32 63 I/O EPI module 0 signal 32
EPI0S33 86 I/O EPI module 0 signal 33
EPI0S34 111 I/O EPI module 0 signal 34
EPI0S35 112 I/O EPI module 0 signal 35
General-Purpose Timers T0CCP0 1
33
85		 I/O 16/32-Bit Timer 0 Capture/Compare/PWM 0
T0CCP1 2
34
86		 I/O 16/32-Bit Timer 0 Capture/Compare/PWM 1
T1CCP0 3
35
94		 I/O 16/32-Bit Timer 1 Capture/Compare/PWM 0
T1CCP1 4
36
93		 I/O 16/32-Bit Timer 1 Capture/Compare/PWM 1
T2CCP0 37
78		 I/O 16/32-Bit Timer 2 Capture/Compare/PWM 0
T2CCP1 38
77		 I/O 16/32-Bit Timer 2 Capture/Compare/PWM 1
T3CCP0 40
76
125		 I/O 16/32-Bit Timer 3 Capture/Compare/PWM 0
T3CCP1 41
75
126		 I/O 16/32-Bit Timer 3 Capture/Compare/PWM 1
T4CCP0 74
95
127		 I/O 16/32-Bit Timer 4 Capture/Compare/PWM 0
T4CCP1 73
96
128		 I/O 16/32-Bit Timer 4 Capture/Compare/PWM 1
T5CCP0 72
91		 I/O 16/32-Bit Timer 5 Capture/Compare/PWM 0
T5CCP1 71
92		 I/O 16/32-Bit Timer 5 Capture/Compare/PWM 1
GPIO, Port A PA0 33 I/O GPIO port A bit 0
PA1 34 I/O GPIO port A bit 1
PA2 35 I/O GPIO port A bit 2
PA3 36 I/O GPIO port A bit 3
PA4 37 I/O GPIO port A bit 4
PA5 38 I/O GPIO port A bit 5
PA6 40 I/O GPIO port A bit 6
PA7 41 I/O GPIO port A bit 7
GPIO, Port B PB0 95 I/O GPIO port B bit 0
PB1 96 I/O GPIO port B bit 1
PB2 91 I/O GPIO port B bit 2
PB3 92 I/O GPIO port B bit 3
PB4 121 I/O GPIO port B bit 4
PB5 120 I/O GPIO port B bit 5
GPIO, Port C PC0 100 I/O GPIO port C bit 0
PC1 99 I/O GPIO port C bit 1
PC2 98 I/O GPIO port C bit 2
PC3 97 I/O GPIO port C bit 3
PC4 25 I/O GPIO port C bit 4
PC5 24 I/O GPIO port C bit 5
PC6 23 I/O GPIO port C bit 6
PC7 22 I/O GPIO port C bit 7
GPIO, Port D PD0 1 I/O GPIO port D bit 0
PD1 2 I/O GPIO port D bit 1
PD2 3 I/O GPIO port D bit 2
PD3 4 I/O GPIO port D bit 3
PD4 125 I/O GPIO port D bit 4
PD5 126 I/O GPIO port D bit 5
PD6 127 I/O GPIO port D bit 6
PD7 128 I/O GPIO port D bit 7
GPIO, Port E PE0 15 I/O GPIO port E bit 0
PE1 14 I/O GPIO port E bit 1
PE2 13 I/O GPIO port E bit 2
PE3 12 I/O GPIO port E bit 3
PE4 123 I/O GPIO port E bit 4
PE5 124 I/O GPIO port E bit 5
GPIO, Port F PF0 42 I/O GPIO port F bit 0
PF1 43 I/O GPIO port F bit 1
PF2 44 I/O GPIO port F bit 2
PF3 45 I/O GPIO port F bit 3
PF4 46 I/O GPIO port F bit 4
GPIO, Port G PG0 49 I/O GPIO port G bit 0
PG1 50 I/O GPIO port G bit 1
GPIO, Port H PH0 29 I/O GPIO port H bit 0
PH1 30 I/O GPIO port H bit 1
PH2 31 I/O GPIO port H bit 2
PH3 32 I/O GPIO port H bit 3
GPIO, Port J PJ0 116 I/O GPIO port J bit 0
PJ1 117 I/O GPIO port J bit 1
GPIO, Port K PK0 18 I/O GPIO port K bit 0
PK1 19 I/O GPIO port K bit 1
PK2 20 I/O GPIO port K bit 2
PK3 21 I/O GPIO port K bit 3
PK4 63 I/O GPIO port K bit 4
PK5 62 I/O GPIO port K bit 5
PK6 61 I/O GPIO port K bit 6
PK7 60 I/O GPIO port K bit 7
GPIO, Port L PL0 81 I/O GPIO port L bit 0
PL1 82 I/O GPIO port L bit 1
PL2 83 I/O GPIO port L bit 2
PL3 84 I/O GPIO port L bit 3
PL4 85 I/O GPIO port L bit 4
PL5 86 I/O GPIO port L bit 5
PL6 94 I/O GPIO port L bit 6
PL7 93 I/O GPIO port L bit 7
GPIO, Port M PM0 78 I/O GPIO port M bit 0
PM1 77 I/O GPIO port M bit 1
PM2 76 I/O GPIO port M bit 2
PM3 75 I/O GPIO port M bit 3
PM4 74 I/O GPIO port M bit 4
PM5 73 I/O GPIO port M bit 5
PM6 72 I/O GPIO port M bit 6
PM7 71 I/O GPIO port M bit 7
GPIO, Port N PN0 107 I/O GPIO port N bit 0
PN1 108 I/O GPIO port N bit 1
PN2 109 I/O GPIO port N bit 2
PN3 110 I/O GPIO port N bit 3
PN4 111 I/O GPIO port N bit 4
PN5 112 I/O GPIO port N bit 5
GPIO, Port P PP0 118 I/O GPIO port P bit 0
PP1 119 I/O GPIO port P bit 1
PP2 103 I/O GPIO port P bit 2
PP3 104 I/O GPIO port P bit 3
PP4 105 I/O GPIO port P bit 4
PP5 106 I/O GPIO port P bit 5
GPIO, Port Q PQ0 5 I/O GPIO port Q bit 0
PQ1 6 I/O GPIO port Q bit 1
PQ2 11 I/O GPIO port Q bit 2
PQ3 27 I/O GPIO port Q bit 3
PQ4 102 I/O GPIO port Q bit 4
Hibernate HIB 65 O An output that indicates the processor is in Hibernate mode
RTCCLK 24
60
104		 O Buffered version of the Hibernation module's 32.768-kHz clock. This signal is not output when the part is in Hibernate mode and before being configured after power-on reset.
TMPR0 71 I/O Tamper signal 0
TMPR1 72 I/O Tamper signal 1
TMPR2 73 I/O Tamper signal 2
TMPR3 74 I/O Tamper signal 3
VBAT 68 - Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup and Hibernation module power-source supply.
WAKE 64 I An external input that brings the processor out of Hibernate mode when asserted
XOSC0 66 I Hibernation module oscillator crystal input or an external clock reference input. This is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC.
XOSC1 67 O Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source.
I2C I2C0SCL 91 I/O I2C module 0 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C0SDA 92 I/O I2C module 0 data
I2C1SCL 49 I/O I2C module 1 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C1SDA 50 I/O I2C module 1 data
I2C2SCL 82
106
112		 I/O I2C module 2 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C2SDA 81
111		 I/O I2C module 2 data
I2C3SCL 63 I/O I2C module 3 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C3SDA 62 I/O I2C module 3 data
I2C4SCL 61 I/O I2C module 4 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C4SDA 60 I/O I2C module 4 data
I2C5SCL 95
121		 I/O I2C module 5 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C5SDA 96
120		 I/O I2C module 5 data
I2C6SCL 40 I/O I2C module 6 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C6SDA 41 I/O I2C module 6 data
I2C7SCL 1
37		 I/O I2C module 7 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C7SDA 2
38		 I/O I2C module 7 data
I2C8SCL 3
35		 I/O I2C module 8 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C8SDA 4
36		 I/O I2C module 8 data
I2C9SCL 33 I/O I2C module 9 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain
I2C9SDA 34 I/O I2C module 9 data
JTAG, SWD, SWO TCK/SWCLK 100 I JTAG/SWD clock
TDI 98 I JTAG TDI
TDO/SWO 97 O JTAG TDO and SWO
TMS/SWDIO 99 I JTAG TMS and SWDIO
PWM M0FAULT0 46 I Motion Control module 0 PWM fault 0
M0FAULT1 61 I Motion Control module 0 PWM fault 1
M0FAULT2 60 I Motion Control module 0 PWM fault 2
M0FAULT3 81 I Motion Control module 0 PWM fault 3
M0PWM0 42 O Motion Control module 0 PWM 0. This signal is controlled by module 0 PWM generator 0.
M0PWM1 43 O Motion Control module 0 PWM 1. This signal is controlled by module 0 PWM generator 0.
M0PWM2 44 O Motion Control module 0 PWM 2. This signal is controlled by module 0 PWM generator 1.
M0PWM3 45 O Motion Control module 0 PWM 3. This signal is controlled by module 0 PWM generator 1.
M0PWM4 49 O Motion Control module 0 PWM 4. This signal is controlled by module 0 PWM generator 2.
M0PWM5 50 O Motion Control module 0 PWM 5. This signal is controlled by module 0 PWM generator 2.
M0PWM6 63 O Motion Control module 0 PWM 6. This signal is controlled by module 0 PWM generator 3.
M0PWM7 62 O Motion Control module 0 PWM 7. This signal is controlled by module 0 PWM generator 3.
Power GND 17
48
55
58
80
114		 - Ground reference for logic and I/O pins
GNDA 10 - The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions
VDD 7
16
26
28
39
47
51
52
69
79
90
101
113
122		 -

Positive supply for I/O and some logic
VDDA 8 - The positive supply for the analog circuits (for example, ADC and Analog Comparators). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in, regardless of system implementation
VDDC 87
115		 -

Positive supply for most of the logic function, including the processor core and most peripherals. The voltage on this pin is 1.2 V and is supplied by the on-chip LDO. The VDDC pins should only be connected to each other and an external capacitor as specified in the LDO electrical specifications.
QEI IDX0 84 I QEI module 0 index
PhA0 82 I QEI module 0 phase A
PhB0 83 I QEI module 0 phase B
SSI SSI0Clk 35 I/O SSI module 0 clock
SSI0Fss 36 I/O SSI module 0 frame signal
SSI0XDAT0 37 I/O SSI module 0 bidirectional data pin 0 (SSI0TX in Legacy SSI mode)
SSI0XDAT1 38 I/O SSI module 0 bidirectional data pin 1 (SSI0RX in Legacy SSI mode)
SSI0XDAT2 40 I/O SSI module 0 bidirectional data pin 2
SSI0XDAT3 41 I/O SSI module 0 bidirectional data pin 3
SSI1Clk 120 I/O SSI module 1 clock
SSI1Fss 121 I/O SSI module 1 frame signal
SSI1XDAT0 123 I/O SSI module 1 bidirectional data pin 0 (SSI1TX in Legacy SSI mode)
SSI1XDAT1 124 I/O SSI module 1 bidirectional data pin 1 (SSI1RX in Legacy SSI mode)
SSI1XDAT2 125 I/O SSI module 1 bidirectional data pin 2
SSI1XDAT3 126 I/O SSI module 1 bidirectional data pin 3
SSI2Clk 4 I/O SSI module 2 clock
SSI2Fss 3 I/O SSI module 2 frame signal
SSI2XDAT0 2 I/O SSI module 2 bidirectional data pin 0 (SSI2TX in Legacy SSI mode)
SSI2XDAT1 1 I/O SSI module 2 bidirectional data pin 1 (SSI2RX in Legacy SSI mode)
SSI2XDAT2 128 I/O SSI module 2 bidirectional data pin 2
SSI2XDAT3 127 I/O SSI module 2 bidirectional data pin 3
SSI3Clk 5
45		 I/O SSI module 3 clock
SSI3Fss 6
44		 I/O SSI module 3 frame signal
SSI3XDAT0 11
43		 I/O SSI module 3 bidirectional data pin 0 (SSI3TX in Legacy SSI mode)
SSI3XDAT1 27
42		 I/O SSI module 3 bidirectional data pin 1 (SSI3RX in Legacy SSI mode)
SSI3XDAT2 46
118		 I/O SSI module 3 bidirectional data pin 2
SSI3XDAT3 119 I/O SSI module 3 bidirectional data pin 3
System Control and Clocks DIVSCLK 102 O An optionally divided reference clock output based on a selected clock source. This signal is not synchronized to the system clock.
NMI 128 I Nonmaskable interrupt
OSC0 88 I Main oscillator crystal input or an external clock reference input
OSC1 89 O Main oscillator crystal output. Leave unconnected when using a single-ended clock source.
RST 70 I System reset input
UART Module 0 U0CTS 30
74
121		 I UART module 0 Clear To Send modem flow control input signal
U0DCD 31
73
104		 I UART module 0 Data Carrier Detect modem status input signal
U0DSR 32
72
105		 I UART module 0 Data Set Ready modem output control line
U0DTR 103 O UART module 0 Data Terminal Ready modem status input signal
U0RI 60
71		 I UART module 0 Ring Indicator modem status input signal
U0RTS 29
120		 O UART module 0 Request to Send modem flow control output signal
U0Rx 33 I UART module 0 receive
U0Tx 34 O UART module 0 transmit
UART Module 1 U1CTS 104
108		 I UART module 1 Clear To Send modem flow control input signal
U1DCD 13
109		 I UART module 1 Data Carrier Detect modem status input signal
U1DSR 14
110		 I UART module 1 Data Set Ready modem output control line
U1DTR 12
111		 O UART module 1 Data Terminal Ready modem status input signal
U1RI 112
123		 I UART module 1 Ring Indicator modem status input signal
U1RTS 15
107		 O UART module 1 Request to Send modem flow control output line
U1Rx 95
102		 I

UART module 1 receive.

U1Tx 96 O UART module 1 transmit
UART Module 2 U2CTS 110
128		 I UART module 2 Clear To Send modem flow control input signal
U2RTS 109
127		 O UART module 2 Request to Send modem flow control output line
U2Rx 40
125		 I UART module 2 receive
U2Tx 41
126		 O UART module 2 transmit
UART Module 3 U3CTS 106
112		 I UART module 3 Clear To Send modem flow control input signal
U3RTS 105
111		 O UART module 3 Request to Send modem flow control output line
U3Rx 37
116		 I UART module 3 receive
U3Tx 38
117		 O UART module 3 transmit
UART Module 4 U4CTS 21 I UART module 4 Clear To Send modem flow control input signal
U4RTS 20 O UART module 4 Request to Send modem flow control output line
U4Rx 18
35		 I UART module 4 receive
U4Tx 19
36		 O UART module 4 transmit
UART Module 5 U5Rx 23 I UART module 5 receive
U5Tx 22 O UART module 5 transmit
UART Module 6 U6Rx 118 I UART module 6 receive
U6Tx 119 O UART module 6 transmit
UART Module 7 U7Rx 25 I UART module 7 receive
U7Tx 24 O UART module 7 transmit
USB USB0CLK 92 O 60-MHz clock to the external PHY
USB0D0 81 I/O USB data 0
USB0D1 82 I/O USB data 1
USB0D2 83 I/O USB data 2
USB0D3 84 I/O USB data 3
USB0D4 85 I/O USB data 4
USB0D5 86 I/O USB data 5
USB0D6 106 I/O USB data 6
USB0D7 105 I/O USB data 7
USB0DIR 104 O Indicates that the external PHY is able to accept data from the USB controller
USB0DM 93 I/O Bidirectional differential data pin (D– per USB specification) for USB0
USB0DP 94 I/O Bidirectional differential data pin (D+ per USB specification) for USB0
USB0EPEN 40
41
127		 O Optionally used in Host mode to control an external power source to supply power to the USB bus
USB0ID 95 I This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side).
USB0NXT 103 O Asserted by the external PHY to throttle all data types
USB0PFLT 41
128		 I Optionally used in Host mode by an external power source to indicate an error state by that power source
USB0STP 91 O Asserted by the USB controller to signal the end of a USB transmit packet or register write operation
USB0VBUS 96 I/O This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing.