JAJSE27
October 2017
MSP432E401Y
PRODUCTION DATA.
1
デバイスの概要
1.1
特長
1.2
アプリケーション
1.3
概要
1.4
機能ブロック図
2
改訂履歴
3
Device Characteristics
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Pin Attributes
4.3
Signal Descriptions
Table 4-3
Signal Descriptions
4.4
GPIO Pin Multiplexing
4.5
Buffer Type
4.6
Connections for Unused Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Recommended DC Operating Conditions
5.5
Recommended GPIO Operating Characteristics
5.6
Recommended Fast GPIO Pad Operating Conditions
5.7
Recommended Slow GPIO Pad Operating Conditions
5.8
GPIO Current Restrictions
5.9
I/O Reliability
5.10
Current Consumption
5.11
Peripheral Current Consumption
5.12
LDO Regulator Characteristics
5.13
Power Dissipation
5.14
Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package
5.15
Timing and Switching Characteristics
5.15.1
Load Conditions
5.15.2
Power Supply Sequencing
5.15.2.1
Power and Brownout
Table 5-3
Power and Brownout Levels
5.15.2.1.1
VDDA Levels
5.15.2.1.2
VDD Levels
5.15.2.1.3
VDDC Levels
5.15.2.1.4
VDD Glitch Response
5.15.2.1.5
VDD Droop Response
5.15.3
Reset Timing
Table 5-4
Reset Characteristics
5.15.4
Clock Specifications
5.15.4.1
PLL Specifications
Table 5-5
Phase Locked Loop (PLL) Characteristics
5.15.4.1.1
PLL Configuration
5.15.4.2
PIOSC Specifications
5.15.4.3
Low-Frequency Oscillator Specifications
Table 5-9
Low-Frequency Oscillator Characteristics
5.15.4.4
Hibernation Low-Frequency Oscillator Specifications
Table 5-10
Hibernation External Oscillator (XOSC) Input Characteristics
Table 5-11
Hibernation Internal Low-Frequency Oscillator Clock Characteristics
5.15.4.5
Main Oscillator Specifications
Table 5-12
Main Oscillator Input Characteristics
5.15.4.6
Main Oscillator Specification WIth ADC
Table 5-14
System Clock Characteristics With ADC Operation
5.15.4.7
System Clock Characteristics With USB Operation
Table 5-15
System Clock Characteristics With USB Operation
5.15.5
Sleep Modes
Table 5-16
Wake From Sleep Characteristics
Table 5-17
Wake From Deep Sleep Characteristics
5.15.6
Hibernation Module
Table 5-18
Hibernation Module Battery Characteristics
Table 5-19
Hibernation Module Characteristics
Table 5-20
Hibernation Module Tamper I/O Characteristics
5.15.7
Flash Memory
Table 5-21
Flash Memory Characteristics
5.15.8
EEPROM
Table 5-22
EEPROM Characteristics
5.15.9
Input/Output Pin Characteristics
Table 5-23
Fast GPIO Module Characteristics
Table 5-24
Slow GPIO Module Characteristics
5.15.9.1
Types of I/O Pins and ESD Protection
5.15.9.1.1
Hibernate WAKE pin
Table 5-25
Pad Voltage and Current Characteristics for Hibernate WAKE Pin
5.15.9.1.2
Nonpower I/O Pins
Table 5-26
Nonpower I/O Pad Voltage and Current Characteristics
5.15.10
External Peripheral Interface (EPI)
Table 5-28
EPI SDRAM Characteristics
Table 5-29
EPI SDRAM Interface Characteristics
Table 5-30
EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
Table 5-31
EPI General-Purpose Interface Characteristics
Table 5-32
EPI PSRAM Interface Characteristics
5.15.11
Analog-to-Digital Converter (ADC)
Table 5-33
Electrical Characteristics for ADC at 1 Msps
Table 5-34
Electrical Characteristics for ADC at 2 Msps
5.15.12
Synchronous Serial Interface (SSI)
Table 5-35
SSI Characteristics
Table 5-36
Bi- and Quad-SSI Characteristics
5.15.13
Inter-Integrated Circuit (I2C) Interface
Table 5-37
I2C Characteristics
5.15.14
Ethernet Controller
5.15.14.1
DC Characteristics
Table 5-38
Ethernet PHY DC Characteristics
5.15.14.2
Clock Characteristics for Ethernet
Table 5-39
MOSC 25-MHz Crystal Specification
Table 5-40
MOSC Single-Ended 25-MHz Oscillator Specification
5.15.14.3
AC Characteristics
Table 5-41
Ethernet Controller Enable and Software Reset Timing
Table 5-42
100Base-TX Transmit Timing
Table 5-43
10Base-T Normal Link Pulse Timing
Table 5-44
Auto-Negotiation Fast Link Pulse (FLP) Timing
Table 5-45
100Base-TX Signal Detect Timing
5.15.15
Universal Serial Bus (USB) Controller
Table 5-46
ULPI Interface Timing
5.15.16
Analog Comparator
Table 5-47
Analog Comparator Characteristics
Table 5-48
Analog Comparator Characteristics
Table 5-49
Analog Comparator Voltage Reference Characteristics
Table 5-50
Analog Comparator Voltage Reference Characteristics
5.15.17
Pulse-Width Modulator (PWM)
Table 5-51
PWM Timing Characteristics
5.15.18
Emulation and Debug
Table 5-52
JTAG Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Arm Cortex-M4F Processor Core
6.3.1
Processor Core
6.3.2
System Timer (SysTick)
6.3.3
Nested Vectored Interrupt Controller (NVIC)
6.3.4
System Control Block (SCB)
6.3.5
Memory Protection Unit (MPU)
6.3.6
Floating-Point Unit (FPU)
6.4
On-Chip Memory
6.4.1
SRAM
6.4.2
Flash Memory
6.4.3
ROM
6.4.4
EEPROM
6.4.5
Memory Map
6.5
Peripherals
6.5.1
External Peripheral Interface (EPI)
6.5.2
Cyclical Redundancy Check (CRC)
6.5.3
Advanced Encryption Standard (AES) Accelerator
6.5.4
Data Encryption Standard (DES) Accelerator
6.5.5
Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
6.5.6
Serial Communications Peripherals
6.5.6.1
Ethernet MAC and PHY
6.5.6.2
Controller Area Network (CAN)
6.5.6.3
Universal Serial Bus (USB)
6.5.6.4
Universal Asynchronous Receiver/Transmitter (UART)
6.5.6.5
Inter-Integrated Circuit (I2C)
6.5.6.6
Quad Synchronous Serial Interface (QSSI)
6.5.7
System Integration
6.5.7.1
Direct Memory Access (DMA)
6.5.7.2
System Control and Clocks
6.5.7.3
Programmable Timers
6.5.7.4
Capture Compare PWM (CCP) Pins
6.5.7.5
Hibernation (HIB) Module
6.5.7.6
Watchdog Timers
6.5.7.7
Programmable GPIOs
6.5.8
Advanced Motion Control
6.5.8.1
Pulse Width Modulation (PWM)
6.5.8.2
Quadrature Encoder With Index (QEI) Module
6.5.9
Analog
6.5.9.1
ADC
6.5.9.2
Analog Comparators
6.5.10
JTAG and Arm Serial Wire Debug
6.5.11
Peripheral Memory Map
6.6
Identification
6.7
Boot Modes
7
Applications, Implementation, and Layout
7.1
System Design Guidelines
8
デバイスおよびドキュメントのサポート
8.1
使い始めと次の手順
8.2
デバイスの項目表記
8.3
ツールとソフトウェア
8.4
ドキュメントのサポート
8.5
Community Resources
8.6
商標
8.7
静電気放電に関する注意事項
8.8
Export Control Notice
8.9
Glossary
9
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PDT|128
MPQF828
サーマルパッド・メカニカル・データ
発注情報
jajse27_oa
6.4
On-Chip Memory
The following on-chip memories are supported:
256KB of single-cycle SRAM
1024KB of flash memory
6KB of EEPROM
Internal ROM loaded with SimpleLink SDK software:
Peripheral driver library
Bootloader