JAJSE27 October   2017 MSP432E401Y

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. Table 5-3 Power and Brownout Levels
          2. 5.15.2.1.1 VDDA Levels
          3. 5.15.2.1.2 VDD Levels
          4. 5.15.2.1.3 VDDC Levels
          5. 5.15.2.1.4 VDD Glitch Response
          6. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
        1. Table 5-4 Reset Characteristics
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. Table 5-5 Phase Locked Loop (PLL) Characteristics
          2. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
          1. Table 5-9 Low-Frequency Oscillator Characteristics
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
          1. Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics
          2. Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics
        5. 5.15.4.5 Main Oscillator Specifications
          1. Table 5-12 Main Oscillator Input Characteristics
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
          1. Table 5-14 System Clock Characteristics With ADC Operation
        7. 5.15.4.7 System Clock Characteristics With USB Operation
          1. Table 5-15 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
        1. Table 5-16 Wake From Sleep Characteristics
        2. Table 5-17 Wake From Deep Sleep Characteristics
      6. 5.15.6  Hibernation Module
        1. Table 5-18 Hibernation Module Battery Characteristics
        2. Table 5-19 Hibernation Module Characteristics
        3. Table 5-20 Hibernation Module Tamper I/O Characteristics
      7. 5.15.7  Flash Memory
        1. Table 5-21 Flash Memory Characteristics
      8. 5.15.8  EEPROM
        1. Table 5-22 EEPROM Characteristics
      9. 5.15.9  Input/Output Pin Characteristics
        1. Table 5-23 Fast GPIO Module Characteristics
        2. Table 5-24 Slow GPIO Module Characteristics
        3. 5.15.9.1    Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
            1. Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin
          2. 5.15.9.1.2 Nonpower I/O Pins
            1. Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics
      10. 5.15.10 External Peripheral Interface (EPI)
        1. Table 5-28 EPI SDRAM Characteristics
        2. Table 5-29 EPI SDRAM Interface Characteristics
        3. Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
        4. Table 5-31 EPI General-Purpose Interface Characteristics
        5. Table 5-32 EPI PSRAM Interface Characteristics
      11. 5.15.11 Analog-to-Digital Converter (ADC)
        1. Table 5-33 Electrical Characteristics for ADC at 1 Msps
        2. Table 5-34 Electrical Characteristics for ADC at 2 Msps
      12. 5.15.12 Synchronous Serial Interface (SSI)
        1. Table 5-35 SSI Characteristics
        2. Table 5-36 Bi- and Quad-SSI Characteristics
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
        1. Table 5-37 I2C Characteristics
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
          1. Table 5-38 Ethernet PHY DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
          1. Table 5-39 MOSC 25-MHz Crystal Specification
          2. Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification
        3. 5.15.14.3 AC Characteristics
          1. Table 5-41 Ethernet Controller Enable and Software Reset Timing
          2. Table 5-42 100Base-TX Transmit Timing
          3. Table 5-43 10Base-T Normal Link Pulse Timing
          4. Table 5-44 Auto-Negotiation Fast Link Pulse (FLP) Timing
          5. Table 5-45 100Base-TX Signal Detect Timing
      15. 5.15.15 Universal Serial Bus (USB) Controller
        1. Table 5-46 ULPI Interface Timing
      16. 5.15.16 Analog Comparator
        1. Table 5-47 Analog Comparator Characteristics
        2. Table 5-48 Analog Comparator Characteristics
        3. Table 5-49 Analog Comparator Voltage Reference Characteristics
        4. Table 5-50 Analog Comparator Voltage Reference Characteristics
      17. 5.15.17 Pulse-Width Modulator (PWM)
        1. Table 5-51 PWM Timing Characteristics
      18. 5.15.18 Emulation and Debug
        1. Table 5-52 JTAG Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 Inter-Integrated Circuit (I2C)
        6. 6.5.6.6 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  Advanced Motion Control
        1. 6.5.8.1 Pulse Width Modulation (PWM)
        2. 6.5.8.2 Quadrature Encoder With Index (QEI) Module
      9. 6.5.9  Analog
        1. 6.5.9.1 ADC
        2. 6.5.9.2 Analog Comparators
      10. 6.5.10 JTAG and Arm Serial Wire Debug
      11. 6.5.11 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 使い始めと次の手順
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.4 GPIO Pin Multiplexing

Table 4-4 lists the GPIO pins and their analog and digital alternate functions. The AINx analog signals go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. Other analog signals are 3.3-V tolerant and are connected directly to their circuitry (C0-, C0+, C1 -, C1+, C2-, C2+, USB0VBUS, USB0ID). These signals are configured by clearing the DEN bit in the GPIODEN register. The digital signals are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric encoding shown in Table 4-4.

Table 4-4 GPIO Pins and Alternate Functions

I/OPINANALOG OR SPECIAL FUNCTION (1)DIGITAL FUNCTION (GPIOPCTL PMCx BIT FIELD ENCODING)
1234567811131415
PA0 33 – U0Rx I2C9SCL T0CCP0 – – – CAN0Rx – – – – –
PA1 34 – U0Tx I2C9SDA T0CCP1 – – – CAN0Tx – – – – –
PA2 35 – U4Rx I2C8SCL T1CCP0 – – – – – – – – SSI0Clk
PA3 36 – U4Tx I2C8SDA T1CCP1 – – – – – – – – SSI0Fss
PA4 37 – U3Rx I2C7SCL T2CCP0 – – – – – – – – SSI0XDAT0
PA5 38 – U3Tx I2C7SDA T2CCP1 – – – – – – – – SSI0XDAT1
PA6 40 – U2Rx I2C6SCL T3CCP0 – USB0EPEN – – – – SSI0XDAT2 – EPI0S8
PA7 41 – U2Tx I2C6SDA T3CCP1 – USB0PFLT – – – USB0EPEN SSI0XDAT3 – EPI0S9
PB0 95 USB0ID U1Rx I2C5SCL T4CCP0 – – – CAN1Rx – – – – –
PB1 96 USB0VBUS U1Tx I2C5SDA T4CCP1 – – – CAN1Tx – – – – –
PB2 91 – – I2C0SCL T5CCP0 – – – – – – – USB0STP EPI0S27
PB3 92 – – I2C0SDA T5CCP1 – – – – – – – USB0CLK EPI0S28
PB4 121 AIN10 U0CTS I2C5SCL – – – – – – – – – SSI1Fss
PB5 120 AIN11 U0RTS I2C5SDA – – – – – – – – – SSI1Clk
PC0 100 – TCK SWCLK – – – – – – – – – – –
PC1 99 – TMS SWDIO – – – – – – – – – – –
PC2 98 – TDI – – – – – – – – – – –
PC3 97 – TDO SWO – – – – – – – – – – –
PC4 25 C1- U7Rx – – – – – – – – – – EPI0S7
PC5 24 C1+ U7Tx – – – – – RTCCLK – – – – EPI0S6
PC6 23 C0+ U5Rx – – – – – – – – – – EPI0S5
PC7 22 C0- U5Tx – – – – – – – – – – EPI0S4
PD0 1 AIN15 – I2C7SCL T0CCP0 – C0o – – – – – – SSI2XDAT1
PD1 2 AIN14 – I2C7SDA T0CCP1 – C1o – – – – – – SSI2XDAT0
PD2 3 AIN13 – I2C8SCL T1CCP0 – C2o – – – – – – SSI2Fss
PD3 4 AIN12 – I2C8SDA T1CCP1 – – – – – – – – SSI2Clk
PD4 125 AIN7 U2Rx – T3CCP0 – – – – – – – – SSI1XDAT2
PD5 126 AIN6 U2Tx – T3CCP1 – – – – – – – – SSI1XDAT3
PD6 127 AIN5 U2RTS – T4CCP0 – USB0EPEN – – – – – – SSI2XDAT3
PD7 128 AIN4 U2CTS – T4CCP1 – USB0PFLT – – NMI – – – SSI2XDAT2
PE0 15 AIN3 U1RTS – – – – – – – – – – –
PE1 14 AIN2 U1DSR – – – – – – – – – – –
PE2 13 AIN1 U1DCD – – – – – – – – – – –
PE3 12 AIN0 U1DTR – – – – – – – – – – –
PE4 123 AIN9 U1RI – – – – – – – – – – SSI1XDAT0
PE5 124 AIN8 – – – – – – – – – – – SSI1XDAT1
PF0 42 – – – – – EN0LED0 M0PWM0 – – – – SSI3XDAT1 TRD2
PF1 43 – – – – – EN0LED2 M0PWM1 – – – – SSI3XDAT0 TRD1
PF2 44 – – – – – – M0PWM2 – – – – SSI3Fss TRD0
PF3 45 – – – – – – M0PWM3 – – – – SSI3Clk TRCLK
PF4 46 – – – – – EN0LED1 M0FAULT0 – – – – SSI3XDAT2 TRD3
PG0 49 – – I2C1SCL – – EN0PPS M0PWM4 – – – – – EPI0S11
PG1 50 – – I2C1SDA – – – M0PWM5 – – – – – EPI0S10
PH0 29 – U0RTS – – – – – – – – – – EPI0S0
PH1 30 – U0CTS – – – – – – – – – – EPI0S1
PH2 31 – U0DCD – – – – – – – – – – EPI0S2
PH3 32 – U0DSR – – – – – – – – – – EPI0S3
PJ0 116 – U3Rx – – – EN0PPS – – – – – – –
PJ1 117 – U3Tx – – – – – – – – – – –
PK0 18 AIN16 U4Rx – – – – – – – – – – EPI0S0
PK1 19 AIN17 U4Tx – – – – – – – – – – EPI0S1
PK2 20 AIN18 U4RTS – – – – – – – – – – EPI0S2
PK3 21 AIN19 U4CTS – – – – – – – – – – EPI0S3
PK4 63 – – I2C3SCL – – EN0LED0 M0PWM6 – – – – – EPI0S32
PK5 62 – – I2C3SDA – – EN0LED2 M0PWM7 – – – – – EPI0S31
PK6 61 – – I2C4SCL – – EN0LED1 M0FAULT1 – – – – – EPI0S25
PK7 60 – U0RI I2C4SDA – – RTCCLK M0FAULT2 – – – – – EPI0S24
PL0 81 – – I2C2SDA – – – M0FAULT3 – – – – USB0D0 EPI0S16
PL1 82 – – I2C2SCL – – – PhA0 – – – – USB0D1 EPI0S17
PL2 83 – – – – – C0o PhB0 – – – – USB0D2 EPI0S18
PL3 84 – – – – – C1o IDX0 – – – – USB0D3 EPI0S19
PL4 85 – – – T0CCP0 – – – – – – – USB0D4 EPI0S26
PL5 86 – – – T0CCP1 – – – – – – – USB0D5 EPI0S33
PL6 94 USB0DP – – T1CCP0 – – – – – – – – –
PL7 93 USB0DM – – T1CCP1 – – – – – – – – –
PM0 78 – – – T2CCP0 – – – – – – – – EPI0S15
PM1 77 – – – T2CCP1 – – – – – – – – EPI0S14
PM2 76 – – – T3CCP0 – – – – – – – – EPI0S13
PM3 75 – – – T3CCP1 – – – – – – – – EPI0S12
PM4 74 TMPR3 U0CTS – T4CCP0 – – – – – – – – –
PM5 73 TMPR2 U0DCD – T4CCP1 – – – – – – – – –
PM6 72 TMPR1 U0DSR – T5CCP0 – – – – – – – – –
PM7 71 TMPR0 U0RI – T5CCP1 – – – – – – – – –
PN0 107 – U1RTS – – – – – – – – – – –
PN1 108 – U1CTS – – – – – – – – – – –
PN2 109 – U1DCD U2RTS – – – – – – – – – EPI0S29
PN3 110 – U1DSR U2CTS – – – – – – – – – EPI0S30
PN4 111 – U1DTR U3RTS I2C2SDA – – – – – – – – EPI0S34
PN5 112 – U1RI U3CTS I2C2SCL – – – – – – – – EPI0S35
PP0 118 C2+ U6Rx – – – – – – – – – – SSI3XDAT2
PP1 119 C2- U6Tx – – – – – – – – – – SSI3XDAT3
PP2 103 – U0DTR – – – – – – – – – USB0NXT EPI0S29
PP3 104 – U1CTS U0DCD – – – – RTCCLK – – – USB0DIR EPI0S30
PP4 105 – U3RTS U0DSR – – – – – – – – USB0D7 –
PP5 106 – U3CTS I2C2SCL – – – – – – – – USB0D6 –
PQ0 5 – – – – – – – – – – – SSI3Clk EPI0S20
PQ1 6 – – – – – – – – – – – SSI3Fss EPI0S21
PQ2 11 – – – – – – – – – – – SSI3XDAT0 EPI0S22
PQ3 27 – – – – – – – – – – – SSI3XDAT1 EPI0S23
PQ4 102 – U1Rx – – – – – DIVSCLK – – – – –
(1) The TMPRn signals are digital signals enabled and configured by the Hibernation module. All other signals listed in this column are analog signals.