JAJSE27 October   2017 MSP432E401Y

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. Table 5-3 Power and Brownout Levels
          2. 5.15.2.1.1 VDDA Levels
          3. 5.15.2.1.2 VDD Levels
          4. 5.15.2.1.3 VDDC Levels
          5. 5.15.2.1.4 VDD Glitch Response
          6. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
        1. Table 5-4 Reset Characteristics
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. Table 5-5 Phase Locked Loop (PLL) Characteristics
          2. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
          1. Table 5-9 Low-Frequency Oscillator Characteristics
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
          1. Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics
          2. Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics
        5. 5.15.4.5 Main Oscillator Specifications
          1. Table 5-12 Main Oscillator Input Characteristics
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
          1. Table 5-14 System Clock Characteristics With ADC Operation
        7. 5.15.4.7 System Clock Characteristics With USB Operation
          1. Table 5-15 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
        1. Table 5-16 Wake From Sleep Characteristics
        2. Table 5-17 Wake From Deep Sleep Characteristics
      6. 5.15.6  Hibernation Module
        1. Table 5-18 Hibernation Module Battery Characteristics
        2. Table 5-19 Hibernation Module Characteristics
        3. Table 5-20 Hibernation Module Tamper I/O Characteristics
      7. 5.15.7  Flash Memory
        1. Table 5-21 Flash Memory Characteristics
      8. 5.15.8  EEPROM
        1. Table 5-22 EEPROM Characteristics
      9. 5.15.9  Input/Output Pin Characteristics
        1. Table 5-23 Fast GPIO Module Characteristics
        2. Table 5-24 Slow GPIO Module Characteristics
        3. 5.15.9.1    Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
            1. Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin
          2. 5.15.9.1.2 Nonpower I/O Pins
            1. Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics
      10. 5.15.10 External Peripheral Interface (EPI)
        1. Table 5-28 EPI SDRAM Characteristics
        2. Table 5-29 EPI SDRAM Interface Characteristics
        3. Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
        4. Table 5-31 EPI General-Purpose Interface Characteristics
        5. Table 5-32 EPI PSRAM Interface Characteristics
      11. 5.15.11 Analog-to-Digital Converter (ADC)
        1. Table 5-33 Electrical Characteristics for ADC at 1 Msps
        2. Table 5-34 Electrical Characteristics for ADC at 2 Msps
      12. 5.15.12 Synchronous Serial Interface (SSI)
        1. Table 5-35 SSI Characteristics
        2. Table 5-36 Bi- and Quad-SSI Characteristics
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
        1. Table 5-37 I2C Characteristics
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
          1. Table 5-38 Ethernet PHY DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
          1. Table 5-39 MOSC 25-MHz Crystal Specification
          2. Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification
        3. 5.15.14.3 AC Characteristics
          1. Table 5-41 Ethernet Controller Enable and Software Reset Timing
          2. Table 5-42 100Base-TX Transmit Timing
          3. Table 5-43 10Base-T Normal Link Pulse Timing
          4. Table 5-44 Auto-Negotiation Fast Link Pulse (FLP) Timing
          5. Table 5-45 100Base-TX Signal Detect Timing
      15. 5.15.15 Universal Serial Bus (USB) Controller
        1. Table 5-46 ULPI Interface Timing
      16. 5.15.16 Analog Comparator
        1. Table 5-47 Analog Comparator Characteristics
        2. Table 5-48 Analog Comparator Characteristics
        3. Table 5-49 Analog Comparator Voltage Reference Characteristics
        4. Table 5-50 Analog Comparator Voltage Reference Characteristics
      17. 5.15.17 Pulse-Width Modulator (PWM)
        1. Table 5-51 PWM Timing Characteristics
      18. 5.15.18 Emulation and Debug
        1. Table 5-52 JTAG Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 Inter-Integrated Circuit (I2C)
        6. 6.5.6.6 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  Advanced Motion Control
        1. 6.5.8.1 Pulse Width Modulation (PWM)
        2. 6.5.8.2 Quadrature Encoder With Index (QEI) Module
      9. 6.5.9  Analog
        1. 6.5.9.1 ADC
        2. 6.5.9.2 Analog Comparators
      10. 6.5.10 JTAG and Arm Serial Wire Debug
      11. 6.5.11 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 使い始めと次の手順
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Table 5-34 Electrical Characteristics for ADC at 2 Msps

VREF+ = 3.3 V, fADC = 32 MHz, over operating free-air temperature (unless otherwise noted) (see Figure 5-26 and Figure 5-27)(1)
PARAMETERMINTYPMAXUNIT
Power supply requirements
VDDA ADC supply voltage 2.97 3.3 3.63 V
GNDA ADC ground voltage 0 V
VDDA and GNDA voltage reference
CREF Voltage reference decoupling capacitance 1.0 // 0.01 (2) µF
External voltage reference input
VREFA+ Positive external voltage reference for ADC, when VREF field in the ADCCTL register is 0x1(3) 2.4 VDDA VDDA V
VREFA- Negative external voltage reference for ADC, when VREF field in the ADCCTL register is 0x1 (3) GNDA GNDA 0.3 V
IVREF Current on VREF+ input, using external VREF+ = 3.3 V 330.5 440 µA
ILVREF DC leakage current on VREF+ input when external VREF disabled 2.0 µA
CREF External reference decoupling capacitance (3) 1.0 // 0.01 (2) µF
Analog input
VADCIN Single-ended, full-scale analog input voltage, internal reference(4)(5) 0 VDDA V
Differential, full-scale analog input voltage, internal reference (4)(6) –VDDA VVDDA
Single-ended, full-scale analog input voltage, external reference (3)(5) VREFA- VREFA+
Differential, full-scale analog input voltage, external reference (3)(7) –(VREFA+ – VREFA-) VREFA+ – VREFA-
VINCM Input common-mode voltage, differential mode (8) [(VREFA+ + VREFA-) / 2] ±0.025 V
IL ADC input leakage current(9) 2.0 µA
RADC ADC equivalent input resistance (9) 2.5 kΩ
CADC ADC equivalent input capacitance (9) 10 pF
RS Analog source resistance (9) 250 Ω
Sampling dynamics
fADC ADC conversion clock frequency(10) 32 MHz
fCONV ADC conversion rate 2 Msps
tS ADC sample time 125 ns
tC ADC conversion time (11) 0.5 µs
tLT Latency from trigger to start of conversion 2 ADC clock cycles
System performance when using external reference(12)(13)
N Resolution

12 bits
INL Integral nonlinearity error, over full input range ±1.5 ±3.0 LSB
DNL Differential nonlinearity error, over full input range ±0.8 +2.0/–1.0 (14) LSB
EO Offset error ±1.0 ±3.0 LSB
EG Gain error (15) ±2.0 ±3.0 LSB
ET Total unadjusted error, over full input range (16) ±2.5 ±4.0 LSB
System performance when using internal reference
N Resolution

12 bits
INL Integral nonlinearity error, over full input range ±1.5 ±3.0 LSB
DNL Differential nonlinearity error, over full input range ±0.8 +2.0/–1.0 (14) LSB
EO Offset error ±5.0 ±15.0 LSB
EG Gain error (15) ±10.0 ±30.0 LSB
ET Total unadjusted error, over full input range (16) ±10.0 ±30.0 LSB
Dynamic characteristics(17)(18)
SNRD Signal-to-noise-ratio, differential input, VADCIN: –20 dB FS, 1 kHz (19) 68 72 dB
SDRD Signal-to-distortion ratio, differential input, VADCIN: –3 dB FS, 1 kHz (19)(20)(21) 70 75 dB
SNDRD Signal-to-noise+distortion ratio, differential input, VADCIN: –3 dB FS, 1 kHz (19)(22)(23) 65 70 dB
SNRS Signal-to-noise-ratio, single-ended input, VADCIN: –20 dB FS, 1 kHz (24) 58 65 dB
SDRS Signal-to-distortion ratio, single-ended input, VADCIN: –3 dB FS, 1 kHz (20)(21) 68 72 dB
SNDRS Signal-to-noise+distortion ratio, single-ended input, VADCIN: –3 dB FS, 1 kHz (24)(22)(23) 58 63 dB
(1) Best design practices suggest placing static or quiet digital I/O signals adjacent to sensitive analog inputs to reduce capacitive coupling and crosstalk. Unexpected results can occur if a switching digital I/O is placed adjacent to an ADC input channel or voltage reference input. In addition, analog signals configured adjacent to ADC input channels or reference inputs must meet the RADC equivalent input resistance given in this table and must be band-limited to 100 kHz or lower.
(2) Two capacitors in parallel. These capacitors should be as close to the die as possible.
(3) Assumes external filtering network between VREFA+ and VREFA- as shown in Figure 5-26. External reference noise level must be under 12-bit (–74-dB) full scale input, over input bandwidth, measured at VREFA+ – VREFA-.
(4) Internal reference is connected directly between VDDA and VGNDA (VREFi = VDDA – VGNDA). In this mode, EO, EG, ET, and dynamic specifications are adversely affected due to internal voltage drop and noise on VDDA and GNDA. Internal reference voltage is selected when VREF field in the ADCCTL register is 0x0.
(5) VADCIN = VINP – VINN
(6) With signal common-mode voltage as VDDA / 2.
(7) With signal common-mode voltage as (VREF+ + VREF-) / 2.
(8) This parameter is defined as the average of the differential inputs.
(9) As shown in Figure 5-27, RADC is the total equivalent resistance in the input line all the way up to the sampling node at the input of the ADC.
(10) See Table 5-14 for full ADC clock frequency specification.
(11) ADC conversion time (tC) includes the ADC sample time (tS).
(12) A low-noise environment is assumed to obtain values close to specifications. The board must have good ground isolation between analog and digital grounds, a clean reference voltage is assumed, and input signal must be bandlimited to Nyquist bandwidth. No antialiasing filter is provided internally.
(13) ADC static measurements taken by averaging over several samples. At least 20-sample averaging is assumed to obtain expected typical or maximum specification values.
(14) 12-bit DNL
(15) Gain error is measured at maximum code after compensating for offset. Gain error is equivalent to"Full Scale Error." It can be given in % of slope error, or in LSB, as done here.
(16) Total Unadjusted Error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors (offset error, gain error and INL) at any given ADC code.
(17) A low noise environment is assumed to obtain values close to spec. The board must have good ground isolation between analog and digital grounds and a clean reference voltage. The input signal must be band-limited to Nyquist bandwidth. No antialiasing filter is provided internally.
(18) ADC dynamic characteristics are measured using low-noise board design, with low-noise reference voltage (< –74 dB noise level in signal BW) and low-noise analog supply voltage. Board noise and ground bouncing couple into the ADC and affect dynamic characteristics. Clean external reference must be used to achieve the listed specifications.
(19) Differential signal with correct common-mode voltage, applied between two ADC inputs.
(20) SDR = –THD in dB.
(21) For higher-frequency inputs, expect degradation in SDR.
(22) SNDR = S/(N+D) = SINAD (in dB)
(23) Effective number of bits (ENOB) can be calculated from SNDR: ENOB = (SNDR – 1.76) / 6.02.
(24) Single-ended inputs are more sensitive to board and trace noise than differential inputs; SNR and SNDR measurements on single-ended inputs are highly dependent on how clean the test setup is. If the input signal is not well isolated on the board, higher noise than specified could be seen at the ADC output.
MSP432E401Y adc_vref.gifFigure 5-26 ADC External Reference Filtering
MSP432E401Y adc_input_equiv.gifFigure 5-27 ADC Input Equivalency