SLASFA2 November   2024 MSPM0G3519

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Chart
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
      15.      27
      16.      28
      17.      29
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
        1. 7.9.2.1 SYSOSC Typical Frequency Accuracy
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 DAC
      1. 7.16.1 DAC_Supply Specifications
      2. 7.16.2 DAC Output Specifications
      3. 7.16.3 DAC Dynamic Specifications
      4. 7.16.4 DAC Linearity Specifications
      5. 7.16.5 DAC Timing Specifications
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Gx51x)
    4. 8.4  Security
    5. 8.5  Power Management Unit (PMU)
    6. 8.6  Clock Module (CKM)
    7. 8.7  DMA
    8. 8.8  Events
    9. 8.9  Memory
      1. 8.9.1 Memory Organization
      2. 8.9.2 Peripheral File Map
      3. 8.9.3 Peripheral Interrupt Vector
    10. 8.10 Flash Memory
    11. 8.11 SRAM
    12. 8.12 GPIO
    13. 8.13 IOMUX
    14. 8.14 ADC
    15. 8.15 Temperature Sensor
    16. 8.16 Low-Frequency Sub System (LFSS)
    17. 8.17 VREF
    18. 8.18 COMP
    19. 8.19 DAC
    20. 8.20 TRNG
    21. 8.21 AESADV
    22. 8.22 Keystore
    23. 8.23 CRC-P
    24. 8.24 MATHACL
    25. 8.25 UART
    26. 8.26 I2C
    27. 8.27 SPI
    28. 8.28 CAN-FD
    29. 8.29 IWDT_B
    30. 8.30 WWDT
    31. 8.31 RTC_B
    32. 8.32 Timers (TIMx)
    33. 8.33 Device Analog Connections
    34. 8.34 Input/Output Diagrams
    35. 8.35 Serial Wire Debug Interface
    36. 8.36 Boot Strap Loader (BSL)
    37. 8.37 Device Factory Constants
    38. 8.38 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

8.3.1 Functionality by Operating Mode (MSPM0Gx51x)

Supported functionality in each operating mode is given in Table 8-1.

Functional key:

  • EN: The function is enabled in the specified mode.
  • DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained.
  • OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.
  • NS: The function is not automatically disabled in the specified mode, but it is not supported.
  • OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be re-configured to the desired settings by application software.

Table 8-1 Supported Functionality by Operating Mode
OPERATING MODERUNSLEEPSTOPSTANDBYSHUTDOWN
RUN0RUN1RUN2SLEEP0SLEEP1SLEEP2STOP0STOP1STOP2STANDBY0STANDBY1
OscillatorsSYSOSCENENDISENENDISOPT(1)ENDISDISDISOFF
LFOSC or LFXTEN (LFOSC or LFXT)OFF
HFXTOPTDISDISOPTDISDISDISDISDISDISDISOFF
SYSPLLOPTDISDISOPTDISDISDISDISDISDISDISOFF
ClocksCPUCLK80 MHz32 kHz32 kHzDISOFF
MCLK to PD180 MHz32 kHz32 kHz80 MHz32 kHz32 kHzDISOFF
ULPCLK to PD040 MHz32 kHz32 kHz40 MHz32 kHz32 kHz4 MHz(1)4 MHz32 kHzDISOFF
ULPCLK to TIMG0, TIMG8, TIMG9, TIMG1440 MHz32 kHz32 kHz40 MHz32 kHz32 kHz4 MHz(1)4 MHz32 kHzOFF
RTCCLK32 kHzOFF
MFCLKOPTDISOPTDISOPTDISOFF
MFPCLKOPTDISOPTDISOPTDISOFF
LFCLK32 kHzDISOFF
LFCLK to TIMG0, TIMG8, TIMG9, TIMG1432 kHzOFF
LFCLK MonitorOPTOFF
MCLK MonitorOPTDISOFF
PMUPOR monitorEN
BOR monitorENOFF
Core regulatorFULL DRIVEREDUCED DRIVELOW DRIVEOFF
Core FunctionsCPUENDISOFF
DMAOPTDIS (triggers supported)OFF
FlashENDISOFF
SRAM (Bank 0) EN DIS OFF
SRAM (Bank 1)OPTDIS / OFF OFF
PD1 PeripheralsCRCOPTDISOFF
UART3, UART4, UART5, UART6OPT

DIS

OFF

SPI0, SPI1, SPI2OPT

DIS

OFF

MATHACL

OPTOFF
AESADVOPTOFF
MCAN0, MCAN1OPTOFF
TIMA0, TIMA1OPTOFF
TIMG0, TIMG6, TIMG7, TIMG12OPTOFF
PD0 PeripheralsTIMG0, TIMG8, TIMG9, TIMG14OPTOFF
RTC_BOPTOFF
UART0, UART1, UART7OPTOPT(2)OFF
I2C0, I2C1, I2C2OPTOPT(2)OFF
GPIOA, GPIOB(3)OPTOPT(2)OFF
WWDT0, WWDT1OPTDISOFF
IWDTOPTOFF
AnalogTRNGOPTOFF
ADC0, ADC1(3)OPTNS (triggers supported)OFF
DAC0OPTNSOFF
COMP0, COMP1, COMP2OPTOPT (ULP)OPTOPT (ULP)OPTOPT (ULP)OFF

VREF

OPTOFF

Temperature Sensor

OPT OFF
IOMUX and IO WakeupENDIS w/ WAKE
Wake SourcesN/AANY IRQPD0 IRQIOMUX, NRST, SWD
(1) If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as it was in RUN1, and ULPCLK remains at 32 kHz as it was in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as it was in RUN2, and ULPCLK remains at 32 kHz as it was in RUN2.
(2) When using the STANDBY1 policy for STANDBY, only TIMG0, TIMG8, and the RTC are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked.
(3) For ADCx and GPIO Ports A and B, the digital logic is in PD0 and the register interface is in PD1. These peripherals support fast single-cycle register access when PD1 is active and also support basic operation down to STANDBY mode where PD0 is still active.