SLASFB5A May 2024 – November 2024 MSPM0L1228-Q1 , MSPM0L2228-Q1
PRODUCTION DATA
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The following table describes the functions available on every pin for each device package.
Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits. The IOMUX only supports connecting one IOMUX-managed digital function to the pin at the same time. The PINCM.PF and PINCM.PC in IOMUX are recommended to be set to 0 when non-IOMUX managed functions (such as analog connections) are intended to be used on a pin. However, non-IOMUX managed signals (such as analog inputs and WAKE inputs) can be enabled on a pin at the same time that an IOMUX managed digital function is enabled on the pin, provided there is no contention between the functions. In this case, the designer must verify that no contention exists between the functions enabled on each pin.
BUFFER TYPE | INVERSION CONTROL | DRIVE STRENGTH CONTROL | HYSTERESIS CONTROL | PULLUP RESISTOR | PULLDOWN RESISTOR | WAKEUP LOGIC | Power Domain |
---|---|---|---|---|---|---|---|
SDIO (standard drive) | Y | Y | Y | VDD | |||
SDIO (standard drive) with wake | Y | Y | Y | Y | VDD | ||
HDIO (High drive) | Y | Y | Y | Y | Y | VDD | |
ODIO (5V-tolerant open drain) | Y | Y | Y | Y | VDD | ||
LFSSIO | Y | Y | Y | VBAT |