JAJSDV8E August 2011 – January 2017 OMAP-L132
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This section provides the timing specification for the DDR2/mDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).