JAJSDV8E August 2011 – January 2017 OMAP-L132
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
NO. | 1.2V | 1.1V | 1.0V | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | MIN | MAX | |||||
9 | tc(SPC)S | Cycle Time, SPI0_CLK, All Slave Modes | 40(2) | 50(2) | 60(2) | ns | ||||
10 | tw(SPCH)S | Pulse Width High, SPI0_CLK, All Slave Modes | 18 | 22 | 27 | ns | ||||
11 | tw(SPCL)S | Pulse Width Low, SPI0_CLK, All Slave Modes | 18 | 22 | 27 | ns | ||||
12 | tsu(SOMI_SPC)S | Setup time, transmit data written to SPI before initial clock edge from
master.(3)(4) |
Polarity = 0, Phase = 0,
to SPI0_CLK rising |
2P | 2P | 2P | ns | |||
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
2P | 2P | 2P | |||||||
Polarity = 1, Phase = 0,
to SPI0_CLK falling |
2P | 2P | 2P | |||||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
2P | 2P | 2P | |||||||
13 | td(SPC_SOMI)S | Delay, subsequent bits valid on SPI0_SOMI after transmit edge of SPI0_CLK | Polarity = 0, Phase = 0,
from SPI0_CLK rising |
17 | 20 | 27 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
17 | 20 | 27 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK falling |
17 | 20 | 27 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
17 | 20 | 27 | |||||||
14 | toh(SPC_SOMI)S | Output hold time, SPI0_SOMI valid after receive edge of SPI0_CLK | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5S-6 | 0.5S-16 | 0.5S-20 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK rising |
0.5S-6 | 0.5S-16 | 0.5S-20 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5S-6 | 0.5S-16 | 0.5S-20 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK falling |
0.5S-6 | 0.5S-16 | 0.5S-20 | |||||||
15 | tsu(SIMO_SPC)S | Input Setup Time, SPI0_SIMO valid before receive edge of SPI0_CLK | Polarity = 0, Phase = 0,
to SPI0_CLK falling |
1.5 | 1.5 | 1.5 | ns | |||
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
1.5 | 1.5 | 1.5 | |||||||
Polarity = 1, Phase = 0,
to SPI0_CLK rising |
1.5 | 1.5 | 1.5 | |||||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
1.5 | 1.5 | 1.5 | |||||||
16 | tih(SPC_SIMO)S | Input Hold Time, SPI0_SIMO valid after receive edge of SPI0_CLK | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
4 | 4 | 5 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK rising |
4 | 4 | 5 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
4 | 4 | 5 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK falling |
4 | 4 | 5 |
NO. | PARAMETER | 1.2V | 1.1V | 1.0V | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | MIN | MAX | |||||
17 | td(ENA_SPC)M | Delay from slave assertion of SPI0_ENA active to first SPI0_CLK from master.(3) | Polarity = 0, Phase = 0,
to SPI0_CLK rising |
3P+5 | 3P+5 | 3P+6 | ns | |||
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
0.5M+3P+5 | 0.5M+3P+5 | 0.5M+3P+6 | |||||||
Polarity = 1, Phase = 0,
to SPI0_CLK falling |
3P+5 | 3P+5 | 3P+6 | |||||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
0.5M+3P+5 | 0.5M+3P+5 | 0.5M+3P+6 | |||||||
18 | td(SPC_ENA)M | Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer.(4) | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5M+P+5 | 0.5M+P+5 | 0.5M+P+6 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
P+5 | P+5 | P+6 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5M+P+5 | 0.5M+P+5 | 0.5M+P+6 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
P+5 | P+5 | P+6 |
NO. | PARAMETER | 1.2V | 1.1V | 1.0V | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | MIN | MAX | |||||
19 | td(SCS_SPC)M | Delay from SPI0_SCS active to first SPI0_CLK(3)(4) | Polarity = 0, Phase = 0,
to SPI0_CLK rising |
2P-1 | 2P-2 | 2P-3 | ns | |||
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
0.5M+2P-1 | 0.5M+2P-2 | 0.5M+2P-3 | |||||||
Polarity = 1, Phase = 0,
to SPI0_CLK falling |
2P-1 | 2P-2 | 2P-3 | |||||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
0.5M+2P-1 | 0.5M+2P-2 | 0.5M+2P-3 | |||||||
20 | td(SPC_SCS)M | Delay from final SPI0_CLK edge to master deasserting SPI0_SCS(5)(6) | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5M+P-1 | 0.5M+P-2 | 0.5M+P-3 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
P-1 | P-2 | P-3 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5M+P-1 | 0.5M+P-2 | 0.5M+P-3 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
P-1 | P-2 | P-3 |
NO. | PARAMETER | 1.2V | 1.1V | 1.0V | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | MIN | MAX | |||||
18 | td(SPC_ENA)M | Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer.(3) | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5M+P+5 | 0.5M+P+5 | 0.5M+P+6 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
P+5 | P+5 | P+6 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5M+P+5 | 0.5M+P+5 | 0.5M+P+6 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
P+5 | P+5 | P+6 | |||||||
20 | td(SPC_SCS)M | Delay from final SPI0_CLK edge to
master deasserting SPI0_SCS(4)(5) |
Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5M+P-2 | 0.5M+P-2 | 0.5M+P-3 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
P-2 | P-2 | P-3 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5M+P-2 | 0.5M+P-2 | 0.5M+P-3 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
P-2 | P-2 | P-3 | |||||||
21 | td(SCSL_ENAL)M | Max delay for slave SPI to drive SPI0_ENA valid after master asserts SPI0_SCS to delay the master from beginning the next transfer, | C2TDELAY+P | C2TDELAY+P | C2TDELAY+P | ns | ||||
22 | td(SCS_SPC)M | Delay from SPI0_SCS active to first SPI0_CLK(6)(7)(8) | Polarity = 0, Phase = 0,
to SPI0_CLK rising |
2P-2 | 2P-2 | 2P-3 | ns | |||
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
0.5M+2P-2 | 0.5M+2P-2 | 0.5M+2P-3 | |||||||
Polarity = 1, Phase = 0,
to SPI0_CLK falling |
2P-2 | 2P-2 | 2P-3 | |||||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
0.5M+2P-2 | 0.5M+2P-2 | 0.5M+2P-3 | |||||||
23 | td(ENA_SPC)M | Delay from assertion of SPI0_ENA low to first SPI0_CLK edge.(9) | Polarity = 0, Phase = 0,
to SPI0_CLK rising |
3P+5 | 3P+5 | 3P+6 | ns | |||
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
0.5M+3P+5 | 0.5M+3P+5 | 0.5M+3P+6 | |||||||
Polarity = 1, Phase = 0,
to SPI0_CLK falling |
3P+5 | 3P+5 | 3P+6 | |||||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
0.5M+3P+5 | 0.5M+3P+5 | 0.5M+3P+6 |
NO. | PARAMETER | 1.2V | 1.1V | 1.0V | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | MIN | MAX | |||||
24 | td(SPC_ENAH)S | Delay from final SPI0_CLK edge to slave deasserting SPI0_ENA. | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
1.5P-3 | 2.5P+17.5 | 1.5P-3 | 2.5P+20 | 1.5P-3 | 2.5P+27 | ns |
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
– 0.5M+1.5P-3 | – 0.5M+2.5P+17.5 | – 0.5M+1.5P-3 | – 0.5M+2.5P+20 | – 0.5M+1.5P-3 | – 0.5M+2.5P+27 | ||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
1.5P-3 | 2.5P+17.5 | 1.5P-3 | 2.5P+20 | 1.5P-3 | 2.5P+27 | ||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
– 0.5M+1.5P-3 | – 0.5+2.5P+17.5 | – 0.5M+1.5P-3 | – 0.5+2.5P+20 | – 0.5M+1.5P-3 | – 0.5+2.5P+27 |
NO. | PARAMETER | 1.2V | 1.1V | 1.0V | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | MIN | MAX | |||||
25 | td(SCSL_SPC)S | Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave. | P + 1.5 | P + 1.5 | P + 1.5 | ns | ||||
26 | td(SPC_SCSH)S | Required delay from final SPI0_CLK edge before SPI0_SCS is deasserted. | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5M+P+4 | 0.5M+P+4 | 0.5M+P+5 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
P+4 | P+4 | P+5 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5M+P+4 | 0.5M+P+4 | 0.5M+P+5 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
P+4 | P+4 | P+5 | |||||||
27 | tena(SCSL_SOMI)S | Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid | P+17.5 | P+20 | P+27 | ns | ||||
28 | tdis(SCSH_SOMI)S | Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI | P+17.5 | P+20 | P+27 | ns |
NO. | PARAMETER | 1.2V | 1.1V | 1.0V | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | MIN | MAX | |||||
25 | td(SCSL_SPC)S | Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave. | P + 1.5 | P + 1.5 | P + 1.5 | ns | ||||
26 | td(SPC_SCSH)S | Required delay from final SPI0_CLK edge before SPI0_SCS is deasserted. | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5M+P+4 | 0.5M+P+4 | 0.5M+P+5 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
P+4 | P+4 | P+5 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5M+P+4 | 0.5M+P+4 | 0.5M+P+5 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
P+4 | P+4 | P+5 | |||||||
27 | tena(SCSL_SOMI)S | Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid | P+17.5 | P+20 | P+27 | ns | ||||
28 | tdis(SCSH_SOMI)S | Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI | P+17.5 | P+20 | P+27 | ns | ||||
29 | tena(SCSL_ENA)S | Delay from master deasserting SPI0_SCS to slave driving SPI0_ENA valid | 17.5 | 20 | 27 | ns | ||||
30 | tdis(SPC_ENA)S | Delay from final clock receive edge on SPI0_CLK to slave 3-stating or driving high SPI0_ENA.(3) | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
2.5P+17.5 | 2.5P+20 | 2.5P+27 | ns | |||
Polarity = 0, Phase = 1,
from SPI0_CLK rising |
2.5P+17.5 | 2.5P+20 | 2.5P+27 | |||||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
2.5P+17.5 | 2.5P+20 | 2.5P+27 | |||||||
Polarity = 1, Phase = 1,
from SPI0_CLK falling |
2.5P+17.5 | 2.5P+20 | 2.5P+27 |