JAJSDV8E August 2011 – January 2017 OMAP-L132
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
NO. | 1.2V | 1.1V | 1.0V | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | MIN | MAX | |||||
1 | tc(SPC)M | Cycle Time, SPI1_CLK, All Master Modes | 20(2) | 256P | 30(2) | 256P | 40(2) | 256P | ns | |
2 | tw(SPCH)M | Pulse Width High, SPI1_CLK, All Master Modes | 0.5M-1 | 0.5M-1 | 0.5M-1 | ns | ||||
3 | tw(SPCL)M | Pulse Width Low, SPI1_CLK, All Master Modes | 0.5M-1 | 0.5M-1 | 0.5M-1 | ns | ||||
4 | td(SIMO_SPC)M | Delay, initial data bit valid on SPI1_SIMO to initial edge on SPI1_CLK(3) | Polarity = 0, Phase = 0,
to SPI1_CLK rising |
5 | 5 | 6 | ns | |||
Polarity = 0, Phase = 1,
to SPI1_CLK rising |
-0.5M+5 | -0.5M+5 | -0.5M+6 | |||||||
Polarity = 1, Phase = 0,
to SPI1_CLK falling |
5 | 5 | 6 | |||||||
Polarity = 1, Phase = 1,
to SPI1_CLK falling |
-0.5M+5 | -0.5M+5 | -0.5M+6 | |||||||
5 | td(SPC_SIMO)M | Delay, subsequent bits valid on SPI1_SIMO after transmit edge of SPI1_CLK | Polarity = 0, Phase = 0,
from SPI1_CLK rising |
5 | 5 | 6 | ns | |||
Polarity = 0, Phase = 1,
from SPI1_CLK falling |
5 | 5 | 6 | |||||||
Polarity = 1, Phase = 0,
from SPI1_CLK falling |
5 | 5 | 6 | |||||||
Polarity = 1, Phase = 1,
from SPI1_CLK rising |
5 | 5 | 6 | |||||||
6 | toh(SPC_SIMO)M | Output hold time, SPI1_SIMO valid after receive edge of SPI1_CLK | Polarity = 0, Phase = 0,
from SPI1_CLK falling |
0.5M-3 | 0.5M-3 | 0.5M-3 | ns | |||
Polarity = 0, Phase = 1,
from SPI1_CLK rising |
0.5M-3 | 0.5M-3 | 0.5M-3 | |||||||
Polarity = 1, Phase = 0,
from SPI1_CLK rising |
0.5M-3 | 0.5M-3 | 0.5M-3 | |||||||
Polarity = 1, Phase = 1,
from SPI1_CLK falling |
0.5M-3 | 0.5M-3 | 0.5M-3 | |||||||
7 | tsu(SOMI_SPC)M | Input Setup Time, SPI1_SOMI valid before receive edge of SPI1_CLK | Polarity = 0, Phase = 0,
to SPI1_CLK falling |
1.5 | 1.5 | 1.5 | ns | |||
Polarity = 0, Phase = 1,
to SPI1_CLK rising |
1.5 | 1.5 | 1.5 | |||||||
Polarity = 1, Phase = 0,
to SPI1_CLK rising |
1.5 | 1.5 | 1.5 | |||||||
Polarity = 1, Phase = 1,
to SPI1_CLK falling |
1.5 | 1.5 | 1.5 | |||||||
8 | tih(SPC_SOMI)M | Input Hold Time, SPI1_SOMI valid after receive edge of SPI1_CLK | Polarity = 0, Phase = 0,
from SPI1_CLK falling |
4 | 5 | 6 | ns | |||
Polarity = 0, Phase = 1,
from SPI1_CLK rising |
4 | 5 | 6 | |||||||
Polarity = 1, Phase = 0,
from SPI1_CLK rising |
4 | 5 | 6 | |||||||
Polarity = 1, Phase = 1,
from SPI1_CLK falling |
4 | 5 | 6 |