JAJSDV8E August 2011 – January 2017 OMAP-L132
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
SIGNAL | TYPE(1) | PULL(2) | POWER
GROUP(3) |
DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
GP0 | |||||
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22] | A1 | I/O | CP[0] | A | GPIO Bank 0 |
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21] | B1 | I/O | CP[0] | A | |
AFSR / GP0[13] / PRU0_R31[20] | C2 | I/O | CP[0] | A | |
AFSX / GP0[12] / PRU0_R31[19] | B2 | I/O | CP[0] | A | |
AHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] / PRU0_R31[18] | A2 | I/O | CP[0] | A | |
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] / PRU0_R31[17] | A3 | I/O | CP[0] | A | |
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] / PRU0_R31[16] | D5 | I/O | CP[0] | A | |
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP | F4 | I/O | CP[0] | A | |
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7] | A4 | I/O | CP[1] | A | |
AXR14 / CLKR1 / GP0[6] | B4 | I/O | CP[2] | A | |
AXR13 / CLKX1 / GP0[5] | B3 | I/O | CP[2] | A | |
AXR12 / FSR1 / GP0[4] | C4 | I/O | CP[2] | A | |
AXR11 / FSX1 / GP0[3] | C5 | I/O | CP[2] | A | |
AXR10 / DR1 / GP0[2] | D4 | I/O | CP[2] | A | |
AXR9 / DX1 / GP0[1] | C3 | I/O | CP[2] | A | |
AXR8 / CLKS1 / ECAP1_APWM1 /GP0[0] / PRU0_R31[8] | E4 | I/O | CP[3] | A | |
GP1 | |||||
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7] | D2 | I/O | CP[4] | A | GPIO Bank 1 |
AXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6] | C1 | I/O | CP[5] | A | |
AXR5 / CLKX0 / GP1[13] / MII_TXCLK | D3 | I/O | CP[5] | A | |
AXR4 / FSR0 / GP1[12] / MII_COL | D1 | I/O | CP[5] | A | |
AXR3 / FSX0 / GP1[11] / MII_TXD[3] | E3 | I/O | CP[5] | A | |
AXR2 / DR0 / GP1[10] / MII_TXD[2] | E2 | I/O | CP[5] | A | |
AXR1 / DX0 / GP1[9] / MII_TXD[1] | E1 | I/O | CP[5] | A | |
SPI0_CLK / EPWM0A / GP1[8] / MII_RXCLK | D19 | I/O | CP[7] | A | |
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDCLK / TM64P0_IN12 | E16 | I/O | CP[10] | A | |
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO / TM64P1_IN12 | D17 | I/O | CP[10] | A | |
SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5] | G16 | I/O | CP[11] | A | |
SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4] | G18 | I/O | CP[11] | A | |
SPI1_SCS[5] / UART2_RXD / I2C1_SCL / GP1[3] | F17 | I/O | CP[12] | A | |
SPI1_SCS[4] / UART2_TXD / I2C1_SDA / GP1[2] | F16 | I/O | CP[12] | A | |
SPI1_SCS[3] / UART1_RXD / GP1[1] | E18 | I/O | CP[13] | A | |
SPI1_SCS[2] / UART1_TXD / GP1[0] | F19 | I/O | CP[13] | A | |
GP2 | |||||
SPI1_SCS[1] / EPWM1A / PRU0_R30[8] / GP2[15] / TM64P2_IN12 | F18 | I/O | CP[14] | A | GPIO Bank 2 |
SPI1_SCS[0] / EPWM1B / PRU0_R30[7] / GP2[14] / TM64P3_IN12 | E19 | I/O | CP[14] | A | |
SPI1_CLK / GP2[13] | G19 | I/O | CP[15] | A | |
SPI1_ENA / GP2[12] | H16 | I/O | CP[15] | A | |
SPI1_SOMI / GP2[11] | H17 | I/O | CP[15] | A | |
SPI1_SIMO / GP2[10] | G17 | I/O | CP[15] | A | |
EMA_BA[1] / GP2[9] | A15 | I/O | CP[16] | B | |
EMA_BA[0] / GP2[8] | C15 | I/O | CP[16] | B | |
EMA_CLK / PRU0_R30[5] / GP2[7] / PRU0_R31[5] | B7 | I/O | CP[16] | B | |
EMA_SDCKE / PRU0_R30[4] / GP2[6] / PRU0_R31[4] | D8 | I/O | CP[16] | B | |
EMA_RAS / PRU0_R30[3] / GP2[5] / PRU0_R31[3] | A16 | I/O | CP[16] | B | |
EMA_CAS / PRU0_R30[2] / GP2[4] / PRU0_R31[2] | A9 | I/O | CP[16] | B | |
EMA_WEN_DQM[0] / GP2[3] | C8 | I/O | CP[16] | B | |
EMA_WEN_DQM[1] / GP2[2] | A5 | I/O | CP[16] | B | |
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] / PRU0_R31[1] | B19 | I/O | CP[16] | B | |
EMA_CS[0] / GP2[0] | A18 | I/O | CP[16] | B | |
GP3 | |||||
EMA_CS[2] / GP3[15] | B17 | I/O | CP[16] | B | GPIO Bank 3 |
EMA_CS[3] / GP3[14] | A17 | I/O | CP[16] | B | |
EMA_CS[4] / GP3[13] | F9 | I/O | CP[16] | B | |
EMA_CS[5] / GP3[12] | B16 | I/O | CP[16] | B | |
EMA_WE / GP3[11] | B9 | I/O | CP[16] | B | |
EMA_OE / GP3[10] | B15 | I/O | CP[16] | B | |
EMA_A_RW / GP3[9] | D10 | I/O | CP[16] | B | |
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] / PRU0_R31[0] | B18 | I/O | CP[16] | B | |
EMA_D[15] / GP3[7] | E6 | I/O | CP[17] | B | |
EMA_D[14] / GP3[6] | C7 | I/O | CP[17] | B | |
EMA_D[13] / GP3[5] | B6 | I/O | CP[17] | B | |
EMA_D[12] / GP3[4] | A6 | I/O | CP[17] | B | |
EMA_D[11] / GP3[3] | D6 | I/O | CP[17] | B | |
EMA_D[10] / GP3[2] | A7 | I/O | CP[17] | B | |
EMA_D[9] / GP3[1] | D9 | I/O | CP[17] | B | |
EMA_D[8] / GP3[0] | E10 | I/O | CP[17] | B | |
GP4 | |||||
EMA_D[7] / GP4[15] | D7 | I/O | CP[17] | B | GPIO Bank 4 |
EMA_D[6] / GP4[14] | C6 | I/O | CP[17] | B | |
EMA_D[5] / GP4[13] | E7 | I/O | CP[17] | B | |
EMA_D[4] / GP4[12] | B5 | I/O | CP[17] | B | |
EMA_D[3] / GP4[11] | E8 | I/O | CP[17] | B | |
EMA_D[2] / GP4[10] | B8 | I/O | CP[17] | B | |
EMA_D[1] / GP4[9] | A8 | I/O | CP[17] | B | |
EMA_D[0] / GP4[8] | C9 | I/O | CP[17] | B | |
MMCSD0_CLK / PRU1_R30[31] / GP4[7] | E9 | I/O | CP[18] | B | |
EMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6] | A10 | I/O | CP[18] | B | |
EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5] | B10 | I/O | CP[18] | B | |
EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4] | A11 | I/O | CP[18] | B | |
EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3] | C10 | I/O | CP[18] | B | |
EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2] | E11 | I/O | CP[18] | B | |
EMA_A[17] / MMCSD0_DAT[4] / PRU1_R30[25] / GP4[1] | B11 | I/O | CP[18] | B | |
EMA_A[16] / MMCSD0_DAT[5] / PRU1_R30[24] / GP4[0] | E12 | I/O | CP[18] | B | |
GP5 | |||||
EMA_A[15] / MMCSD0_DAT[6] / PRU1_R30[23] / GP5[15] / PRU1_R31[23] | C11 | I/O | CP[19] | B | GPIO Bank 5 |
EMA_A[14] / MMCSD0_DAT[7] / PRU1_R30[22] / GP5[14] / PRU1_R31[22] | A12 | I/O | CP[19] | B | |
EMA_A[13] / PRU0_R30[21] / PRU1_R30[21] / GP5[13] / PRU1_R31[21] | D11 | I/O | CP[19] | B | |
EMA_A[12] / PRU1_R30[20] / GP5[12] / PRU1_R31[20] | D13 | I/O | CP[19] | B | |
EMA_A[11] / PRU1_R30[19] / GP5[11] / PRU1_R31[19] | B12 | I/O | CP[19] | B | |
EMA_A[10] / PRU1_R30[18] / GP5[10] / PRU1_R31[18] | C12 | I/O | CP[19] | B | |
EMA_A[9] / PRU1_R30[17] / GP5[9] | D12 | I/O | CP[19] | B | |
EMA_A[8] / PRU1_R30[16] / GP5[8] | A13 | I/O | CP[19] | B | |
EMA_A[7] / PRU1_R30[15] / GP5[7] | B13 | I/O | CP[20] | B | |
EMA_A[6] / GP5[6] | E13 | I/O | CP[20] | B | |
EMA_A[5] / GP5[5] | C13 | I/O | CP[20] | B | |
EMA_A[4] / GP5[4] | A14 | I/O | CP[20] | B | |
EMA_A[3] / GP5[3] | D14 | I/O | CP[20] | B | |
EMA_A[2] / GP5[2] | B14 | I/O | CP[20] | B | |
EMA_A[1] / GP5[1] | D15 | I/O | CP[20] | B | |
EMA_A[0] / GP5[0] | C14 | I/O | CP[20] | B | |
GP6 | |||||
RESETOUT / PRU1_R30[14] / GP6[15] | T17 | I/O | CP[21] | C | GPIO Bank 6 |
CLKOUT / PRU1_R30[13] / GP6[14] | T18 | I/O | CP[22] | C | |
PRU0_R30[31] / PRU1_R30[12] / GP6[13] | R17 | I/O | CP[23] | C | |
PRU0_R30[30] / PRU1_R30[11] / GP6[12] | R16 | I/O | CP[23] | C | |
PRU0_R30[29] / GP6[11] | U17 | I/O | CP[24] | C | |
PRU0_R30[28] / GP6[10] | W15 | I/O | CP[24] | C | |
PRU0_R30[27] / GP6[9] | U16 | I/O | CP[24] | C | |
PRU0_R30[26] / /GP6[8] / PRU1_R31[17] | T15 | I/O | CP[24] | C | |
PRU1_R30[10]GP6[7] | W14 | I/O | CP[25] | C | |
PRU1_R30[9] / GP6[6] / PRU1_R31[16] | V15 | I/O | CP[25] | C | |
GP6[5] / PRU1_R31[0] | P17 | I/O | CP[27] | C | |
MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] / PRU1_R31[4] | H3 | I/O | CP[30] | C | |
MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] / PRU1_R31[3] | K3 | I/O | CP[30] | C | |
MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] / PRU1_R31[2] | J3 | I/O | CP[30] | C | |
PRU1_R30[0] / GP6[1] / PRU1_R31[1] | K4 | I/O | CP[30] | C | |
GP6[0] / PRU1_R31[28] | R5 | I/O | CP[31] | C | |
GP7 | |||||
GP7[15] / PRU1_R31[15] | U2 | I/O | CP[28] | C | GPIO Bank 7 |
GP7[14] / PRU1_R31[14] | U1 | I/O | CP[28] | C | |
GP7[13] / PRU1_R31[13] | V3 | I/O | CP[28] | C | |
GP7[12] / PRU1_R31[12] | V2 | I/O | CP[28] | C | |
GP7[11] / PRU1_R31[11] | V1 | I/O | CP[28] | C | |
GP7[10] / PRU1_R31[10] | W3 | I/O | CP[28] | C | |
GP7[9] / PRU1_R31[9] | W2 | I/O | CP[28] | C | |
GP7[8] / PRU1_R31[8] | W1 | I/O | CP[28] | C | |
GP7[7] / BOOT[7] | P4 | I/O | CP[29] | C | |
GP7[6] / BOOT[6] | R3 | I/O | CP[29] | C | |
GP7[5]/ BOOT[5] | R2 | I/O | CP[29] | C | |
GP7[4] / BOOT[4] | R1 | I/O | CP[29] | C | |
GP7[3] / BOOT[3] | T3 | I/O | CP[29] | C | |
GP7[2] / BOOT[2] | T2 | I/O | CP[29] | C | |
GP7[1] / BOOT[1] | T1 | I/O | CP[29] | C | |
GP7[0] / BOOT[0] | U3 | I/O | CP[29] | C | |
GP8 | |||||
PRU0_R30[25] / MMCSD1_DAT[0] / GP8[15] / PRU1_R31[27] | G1 | I/O | CP30] | C | GPIO Bank 8 |
PRU0_R30[24] / MMCSD1_CLK / GP8[14] / PRU1_R31[26] | G2 | I/O | CP[30] | C | |
PRU0_R30[23] / MMCSD1_CMD / GP8[13] / PRU1_R31[25] | J4 | I/O | CP[30] | C | |
PRU0_R30[22] / PRU1_R30[8] / GP8[12] / PRU1_R31[24] | G3 | I/O | CP[30] | C | |
MMCSD1_DAT[7] / PRU1_R30[7] / GP8[11] | F1 | I/O | CP[31] | C | |
MMCSD1_DAT[6] / PRU1_R30[6] / GP8[10] / PRU1_R31[7] | F2 | I/O | CP[31] | C | |
MMCSD1_DAT[5] / PRU1_R30[5] / GP8[9] / PRU1_R31[6] | H4 | I/O | CP[31] | C | |
MMCSD1_DAT[4] / PRU1_R30[4] / GP8[8] / PRU1_R31[5] | G4 | I/O | CP[31] | C | |
AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] / CLKS0 | F3 | I/O | CP[6] | A | |
SPI0_SOMI / EPWMSYNCI / GP8[6] / MII_RXER | C16 | I/O | CP[7] | A | |
SPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS | C18 | I/O | CP[7] | A | |
SPI0_SCS[5] / UART0_RXD / GP8[4] / MII_RXD[3] | C19 | I/O | CP[8] | A | |
SPI0_SCS[4] / UART0_TXD / GP8[3] / MII_RXD[2] | D18 | I/O | CP[8] | A | |
SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] | E17 | I/O | CP[9] | A | |
SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0] | D16 | I/O | CP[9] | A | |
RTCK / GP8[0](5) | K17 | I/O | IPD | B |