JAJSDV8E August   2011  – January 2017 OMAP-L132

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 DSP Subsystem
      1. 3.4.1 C674x DSP CPU Description
      2. 3.4.2 DSP Memory Mapping
        1. 3.4.2.1 ARM Internal Memories
        2. 3.4.2.2 External Memories
        3. 3.4.2.3 DSP Internal Memories
        4. 3.4.2.4 C674x CPU
    5. 3.5 Memory Map Summary
      1. Table 3-4 OMAP-L132 Top Level Memory Map
    6. 3.6 Pin Assignments
      1. 3.6.1 Pin Map (Bottom View)
    7. 3.7 Pin Multiplexing Control
    8. 3.8 Terminal Functions
      1. 3.8.1  Device Reset, NMI and JTAG
      2. 3.8.2  High-Frequency Oscillator and PLL
      3. 3.8.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.8.4  DEEPSLEEP Power Control
      5. 3.8.5  External Memory Interface A (EMIFA)
      6. 3.8.6  DDR2/mDDR Controller
      7. 3.8.7  Serial Peripheral Interface Modules (SPI)
      8. 3.8.8  Programmable Real-Time Unit (PRU)
      9. 3.8.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.8.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.8.11 Boot
      12. 3.8.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.8.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.8.14 Timers
      15. 3.8.15 Multichannel Audio Serial Ports (McASP)
      16. 3.8.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.8.17 Universal Serial Bus Modules (USB0)
      18. 3.8.18 Ethernet Media Access Controller (EMAC)
      19. 3.8.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.8.20 General Purpose Input Output
      21. 3.8.21 Reserved and No Connect
      22. 3.8.22 Supply and Ground
    9. 3.9 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments
        5. 6.7.1.5 AINTC Memory Map
      2. 6.7.2 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Power Domain States
        2. 6.8.1.2 Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-21 Timing Requirements for EMIFA SDRAM Interface
        2. Table 6-22 Switching Characteristics for EMIFA SDRAM Interface
        3. Table 6-23 Timing Requirements for EMIFA Asynchronous Memory Interface
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-42 Timing Requirements for MMC/SD (see and )
        2. Table 6-43 Switching Characteristics for MMC/SD (see through )
    14. 6.14 Multichannel Audio Serial Port (McASP)
      1. 6.14.1 McASP Peripheral Registers Description(s)
      2. 6.14.2 McASP Electrical Data/Timing
        1. 6.14.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-47 Timing Requirements for McASP0 (1.2V, 1.1V)
          2. Table 6-48 Timing Requirements for McASP0 (1.0V)
          3. Table 6-49 Switching Characteristics for McASP0 (1.2V, 1.1V)
          4. Table 6-50 Switching Characteristics for McASP0 (1.0V)
    15. 6.15 Multichannel Buffered Serial Port (McBSP)
      1. 6.15.1 McBSP Peripheral Register Description(s)
      2. 6.15.2 McBSP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Buffered Serial Port (McBSP) Timing
          1. Table 6-52 Timing Requirements for McBSP0 [1.2V, 1.1V] (see )
          2. Table 6-53 Timing Requirements for McBSP0 [1.0V] (see )
          3. Table 6-54 Switching Characteristics for McBSP0 [1.2V, 1.1V] (see )
          4. Table 6-55 Switching Characteristics for McBSP0 [1.0V] (see )
          5. Table 6-56 Timing Requirements for McBSP1 [1.2V, 1.1V] (see )
          6. Table 6-57 Timing Requirements for McBSP1 [1.0V] (see )
          7. Table 6-58 Switching Characteristics for McBSP1 [1.2V, 1.1V] (see )
          8. Table 6-59 Switching Characteristics for McBSP1 [1.0V] (see )
          9. Table 6-60 Timing Requirements for McBSP0 FSR When GSYNC = 1 (see )
          10. Table 6-61 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
    16. 6.16 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.16.1 SPI Peripheral Registers Description(s)
      2. 6.16.2 SPI Electrical Data/Timing
        1. 6.16.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-63 General Timing Requirements for SPI0 Master Modes
          2. Table 6-64 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-71 General Timing Requirements for SPI1 Master Modes
          4. Table 6-72 General Timing Requirements for SPI1 Slave Modes
          5. Table 6-73 Additional SPI1 Master Timings, 4-Pin Enable Option
          6. Table 6-74 Additional SPI1 Master Timings, 4-Pin Chip Select Option
    17. 6.17 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.17.1 I2C Device-Specific Information
      2. 6.17.2 I2C Peripheral Registers Description(s)
      3. 6.17.3 I2C Electrical Data/Timing
        1. 6.17.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-80 Timing Requirements for I2C Input
          2. Table 6-81 Switching Characteristics for I2C
    18. 6.18 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.18.1 UART Peripheral Registers Description(s)
      2. 6.18.2 UART Electrical Data/Timing
        1. Table 6-83 Timing Requirements for UART Receive (see )
        2. Table 6-84 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    19. 6.19 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.19.1 USB0 [USB2.0] Electrical Data/Timing
        1. Table 6-86 Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see )
    20. 6.20 Ethernet Media Access Controller (EMAC)
      1. 6.20.1 EMAC Peripheral Register Description(s)
        1. 6.20.1.1 EMAC Electrical Data/Timing
          1. Table 6-91 Timing Requirements for MII_RXCLK (see )
          2. Table 6-92 Timing Requirements for MII_TXCLK (see )
          3. Table 6-93 Timing Requirements for EMAC MII Receive 10/100 Mbit/s (see )
          4. Table 6-94 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (see )
    21. 6.21 Management Data Input/Output (MDIO)
      1. 6.21.1 MDIO Register Description(s)
      2. 6.21.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-98 Timing Requirements for MDIO Input (see and )
        2. Table 6-99 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    22. 6.22 Enhanced Capture (eCAP) Peripheral
      1. Table 6-101 Timing Requirements for Enhanced Capture (eCAP)
      2. Table 6-102 Switching Characteristics Over Recommended Operating Conditions for eCAP
    23. 6.23 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.23.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-104 Timing Requirements for eHRPWM
        2. Table 6-105 Switching Characteristics Over Recommended Operating Conditions for eHRPWM
      2. 6.23.2 Trip-Zone Input Timing
    24. 6.24 Timers
      1. 6.24.1 Timer Electrical Data/Timing
        1. Table 6-107 Timing Requirements for Timer Input (see )
        2. Table 6-108 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    25. 6.25 Real Time Clock (RTC)
      1. 6.25.1 Clock Source
      2. 6.25.2 Real-Time Clock Register Descriptions
    26. 6.26 General-Purpose Input/Output (GPIO)
      1. 6.26.1 GPIO Register Description(s)
      2. 6.26.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-111 Timing Requirements for GPIO Inputs (see )
        2. Table 6-112 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.26.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-113 Timing Requirements for External Interrupts (see )
    27. 6.27 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.27.1 PRUSS Register Descriptions
    28. 6.28 Emulation Logic
      1. 6.28.1 JTAG Port Description
      2. 6.28.2 Scan Chain Configuration Parameters
      3. 6.28.3 Initial Scan Chain Configuration
        1. 6.28.3.1 Adding TAPS to the Scan Chain
      4. 6.28.4 IEEE 1149.1 JTAG
        1. 6.28.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
        2. 6.28.4.2 JTAG Test-Port Electrical Data/Timing
          1. Table 6-125 Timing Requirements for JTAG Test Port (see )
          2. Table 6-126 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
      5. 6.28.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZWT Package
    2. 8.2 Packaging Information

パッケージ・オプション

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  • ZWT|361
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発注情報

3.1 Device Characteristics

Table 3-1 provides an overview of the device. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count.

Table 3-1 Characteristics of OMAP-L132

HARDWARE FEATURES OMAP-L132
Peripherals
Not all peripherals pins are available at the same time (for more detail, see the Device Configurations section). 		DDR2/mDDR Memory Controller DDR2, 16-bit bus width, up to 156 MHz
Mobile DDR, 16-bit bus width, up to 150 MHz
EMIFA Asynchronous (8/16-bit bus width) RAM, Flash,
16-bit SDRAM, NOR, NAND
Flash Card Interface 2 MMC and SD cards supported.
EDMA3 64 independent channels, 16 QDMA channels,
2 channel controllers, 3 transfer controllers
Timers 4 64-Bit General Purpose (each configurable as 2 separate 32-bit timers, one configurable as Watch Dog)
UART 3 (each with RTS and CTS flow control)
SPI 2 (Each with one hardware chip select)
I2C 2 (both Master/Slave)
Multichannel Audio Serial Port [McASP] 1 (each with transmit/receive, FIFO buffer, 16 serializers)
Multichannel Buffered Serial Port [McBSP] 2 (each with transmit/receive, FIFO buffer, 16)
10/100 Ethernet MAC with Management Data I/O 1 (MII or RMII Interface)
eHRPWM 4 Single Edge, 4 Dual Edge Symmetric, or
2 Dual Edge Asymmetric Outputs
eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY
General-Purpose Input/Output Port 9 banks of 16-bit
PRU Subsystem (PRUSS) 2 Programmable PRU Cores
On-Chip Memory Size (Bytes) 488KB RAM
Organization DSP
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
DSP Memories can be made accessible to ARM, EDMA3, and other peripherals.
ARM
16KB I-Cache
16KB D-Cache
8KB RAM (Vector Table)
64KB ROM
ADDITIONAL SHARED MEMORY
128KB RAM
C674x CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1400
C674x Megamodule Revision Revision ID Register (MM_REVID[15:0]) 0x0000
JTAG BSDL_ID DEVIDR0 Register see Section 6.28.4.1, JTAG Peripheral Register Description
CPU Frequency MHz 674x DSP 200 MHz (1.2V)
ARM926 200 MHz (1.2V)
Voltage Core (V) 1.2 V nominal
I/O (V) 1.8V or 3.3 V
Packages 16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT)
Product Status(1) Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 200 MHz versions - PD
(1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.