SPRS563G September 2008 – June 2014 OMAP-L137
PRODUCTION DATA.
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This device supports a variety of boot modes through an internal ROM bootloader. This device does not support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by the values of the BOOT pins
The following boot modes are supported:
The following system level features of the chip are controlled by the SYSCFG peripheral:
Many registers are accessible only by a host (ARM or DSP) when it is operating in its privileged mode. (ex. from the kernel, but not from user space code).
BYTE ADDRESS | ACRONYM | REGISTER DESCRIPTION | ACCESS |
---|---|---|---|
0x01C1 4000 | REVID | Revision Identification Register | — |
0x01C14008 | DIEIDR0 | Device Identification Register 0 | — |
0x01C1 400C | DIEIDR1 | Device Identification Register 1 | — |
0x01C1 4010 | DIEIDR2 | Device Identification Register 2 | — |
0x01C1 4014 | DIEIDR3 | Device Identification Register 3 | — |
0x01C1 4018 | DEVIDR0 | JTAG Identification Register | — |
0x01C1 4020 | BOOTCFG | Boot Configuration Register | Privileged mode |
0x01C1 4024 | CHIPREVID | Silicon Revision Identification Register | Privileged mode |
0x01C1 4038 | KICK0R | Kick 0 Register | Privileged mode |
0x01C1 403C | KICK1R | Kick 1 Register | Privileged mode |
0x01C1 4040 | HOST0CFG | Host 0 Configuration Register | — |
0x01C1 4044 | HOST1CFG | Host 1 Configuration Register | — |
0x01C1 40E0 | IRAWSTAT | Interrupt Raw Status/Set Register | Privileged mode |
0x01C1 40E4 | IENSTAT | Interrupt Enable Status/Clear Register | Privileged mode |
0x01C1 40E8 | IENSET | Interrupt Enable Register | Privileged mode |
0x01C1 40EC | IENCLR | Interrupt Enable Clear Register | Privileged mode |
0x01C1 40F0 | EOI | End of Interrupt Register | Privileged mode |
0x01C1 40F4 | FLTADDRR | Fault Address Register | Privileged mode |
0x01C1 40F8 | FLTSTAT | Fault Status Register | — |
0x01C1 4110 | MSTPRI0 | Master Priority 0 Register | Privileged mode |
0x01C1 4114 | MSTPRI1 | Master Priority 1 Register | Privileged mode |
0x01C1 4118 | MSTPRI2 | Master Priority 2 Register | Privileged mode |
0x01C1 4120 | PINMUX0 | Pin Multiplexing Control 0 Register | Privileged mode |
0x01C1 4124 | PINMUX1 | Pin Multiplexing Control 1 Register | Privileged mode |
0x01C1 4128 | PINMUX2 | Pin Multiplexing Control 2 Register | Privileged mode |
0x01C1 412C | PINMUX3 | Pin Multiplexing Control 3 Register | Privileged mode |
0x01C1 4130 | PINMUX4 | Pin Multiplexing Control 4 Register | Privileged mode |
0x01C1 4134 | PINMUX5 | Pin Multiplexing Control 5 Register | Privileged mode |
0x01C1 4138 | PINMUX6 | Pin Multiplexing Control 6 Register | Privileged mode |
0x01C1 413C | PINMUX7 | Pin Multiplexing Control 7 Register | Privileged mode |
0x01C1 4140 | PINMUX8 | Pin Multiplexing Control 8 Register | Privileged mode |
0x01C1 4144 | PINMUX9 | Pin Multiplexing Control 9 Register | Privileged mode |
0x01C1 4148 | PINMUX10 | Pin Multiplexing Control 10 Register | Privileged mode |
0x01C1 414C | PINMUX11 | Pin Multiplexing Control 11 Register | Privileged mode |
0x01C1 4150 | PINMUX12 | Pin Multiplexing Control 12 Register | Privileged mode |
0x01C1 4154 | PINMUX13 | Pin Multiplexing Control 13 Register | Privileged mode |
0x01C1 4158 | PINMUX14 | Pin Multiplexing Control 14 Register | Privileged mode |
0x01C1 415C | PINMUX15 | Pin Multiplexing Control 15 Register | Privileged mode |
0x01C1 4160 | PINMUX16 | Pin Multiplexing Control 16 Register | Privileged mode |
0x01C1 4164 | PINMUX17 | Pin Multiplexing Control 17 Register | Privileged mode |
0x01C1 4168 | PINMUX18 | Pin Multiplexing Control 18 Register | Privileged mode |
0x01C1 416C | PINMUX19 | Pin Multiplexing Control 19 Register | Privileged mode |
0x01C1 4170 | SUSPSRC | Suspend Source Register | Privileged mode |
0x01C1 4174 | CHIPSIG | Chip Signal Register | — |
0x01C1 4178 | CHIPSIG_CLR | Chip Signal Clear Register | — |
0x01C1 417C | CFGCHIP0 | Chip Configuration 0 Register | Privileged mode |
0x01C1 4180 | CFGCHIP1 | Chip Configuration 1 Register | Privileged mode |
0x01C1 4184 | CFGCHIP2 | Chip Configuration 2 Register | Privileged mode |
0x01C1 4188 | CFGCHIP3 | Chip Configuration 3 Register | Privileged mode |
0x01C1 418C | CFGCHIP4 | Chip Configuration 4 Register | Privileged mode |
Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot and configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor: