JAJSDV4 データシート

JAJSDV4J June 2009 – January 2017 OMAP-L138

PRODUCTION DATA.

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）

ZCE|361
ZWT|361

サーマルパッド・メカニカル・データ

発注情報

6.10.2 EMIFA Synchronous DRAM Memory Support

The device supports 16-bit SDRAM in addition to the asynchronous memories listed in Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are supported are:

One, Two, and Four Bank SDRAM devices
Devices with Eight, Nine, Ten, and Eleven Column Address
CAS Latency of two or three clock cycles
Sixteen Bit Data Bus Width

Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory contents; since the SDRAM will continue to refresh itself even without clocks from the device. Powerdown mode achieves even lower power, except the device must periodically wake the SDRAM up and issue refreshes if data retention is required.

Finally, note that the EMIFA does not support Mobile SDRAM devices.

Table 6-19 shows the supported SDRAM configurations for EMIFA.

Table 6-19 EMIFA Supported SDRAM Configurations⁽¹⁾

SDRAM Memory Data Bus Width (bits)	Number of Memories	EMIFA Data Bus Size (bits)	Rows	Columns	Banks	Total Memory (Mbits)	Total Memory (Mbytes)	Memory Density (Mbits)
	1	16	16	8	1	256	32	256
	1	16	16	8	2	512	64	512
	1	16	16	8	4	1024	128	1024
	1	16	16	9	1	512	64	512
	1	16	16	9	2	1024	128	1024
16	1	16	16	9	4	2048	256	2048
	1	16	16	10	1	1024	128	1024
	1	16	16	10	2	2048	256	2048
	1	16	16	10	4	4096	512	4096
	1	16	16	11	1	2048	256	2048
	1	16	16	11	2	4096	512	4096
	1	16	15	11	4	4096	512	4096
	2	16	16	8	1	256	32	128
	2	16	16	8	2	512	64	256
	2	16	16	8	4	1024	128	512
	2	16	16	9	1	512	64	256
	2	16	16	9	2	1024	128	512
8	2	16	16	9	4	2048	256	1024
	2	16	16	10	1	1024	128	512
	2	16	16	10	2	2048	256	1024
	2	16	16	10	4	4096	512	2048
	2	16	16	11	1	2048	256	1024
	2	16	16	11	2	4096	512	2048
	2	16	15	11	4	4096	512	2048

(1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of supporting these densities are not available in the market.