JAJSDV4J
June 2009 – January 2017
OMAP-L138
PRODUCTION DATA.
1
デバイスの概要
1.1
特長
1.2
アプリケーション
1.3
概要
1.4
機能ブロック図
2
Revision History
3
Device Comparison
3.1
Device Characteristics
3.2
Device Compatibility
3.3
ARM Subsystem
3.3.1
ARM926EJ-S RISC CPU
3.3.2
CP15
3.3.3
MMU
3.3.4
Caches and Write Buffer
3.3.5
Advanced High-Performance Bus (AHB)
3.3.6
Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
3.3.7
ARM Memory Mapping
3.4
DSP Subsystem
3.4.1
C674x DSP CPU Description
3.4.2
DSP Memory Mapping
3.4.2.1
ARM Internal Memories
3.4.2.2
External Memories
3.4.2.3
DSP Internal Memories
3.4.2.4
C674x CPU
3.5
Memory Map Summary
Table 3-4
Top Level Memory Map
3.6
Pin Assignments
3.6.1
Pin Map (Bottom View)
3.7
Pin Multiplexing Control
3.8
Terminal Functions
3.8.1
Device Reset, NMI and JTAG
3.8.2
High-Frequency Oscillator and PLL
3.8.3
Real-Time Clock and 32-kHz Oscillator
3.8.4
DEEPSLEEP Power Control
3.8.5
External Memory Interface A (EMIFA)
3.8.6
DDR2/mDDR Controller
3.8.7
Serial Peripheral Interface Modules (SPI)
3.8.8
Programmable Real-Time Unit (PRU)
3.8.9
Enhanced Capture/Auxiliary PWM Modules (eCAP0)
3.8.10
Enhanced Pulse Width Modulators (eHRPWM)
3.8.11
Boot
3.8.12
Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
3.8.13
Inter-Integrated Circuit Modules(I2C0, I2C1)
3.8.14
Timers
3.8.15
Multichannel Audio Serial Ports (McASP)
3.8.16
Multichannel Buffered Serial Ports (McBSP)
3.8.17
Universal Serial Bus Modules (USB0, USB1)
3.8.18
Ethernet Media Access Controller (EMAC)
3.8.19
Multimedia Card/Secure Digital (MMC/SD)
3.8.20
Liquid Crystal Display Controller(LCD)
3.8.21
Serial ATA Controller (SATA)
3.8.22
Universal Host-Port Interface (UHPI)
3.8.23
Universal Parallel Port (uPP)
3.8.24
Video Port Interface (VPIF)
3.8.25
General Purpose Input Output
3.8.26
Reserved and No Connect
3.8.27
Supply and Ground
3.9
Unused Pin Configurations
4
Device Configuration
4.1
Boot Modes
4.2
SYSCFG Module
4.3
Pullup/Pulldown Resistors
5
Specifications
5.1
Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
5.2
Handling Ratings
5.3
Recommended Operating Conditions
5.4
Notes on Recommended Power-On Hours (POH)
5.5
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
6
Peripheral Information and Electrical Specifications
6.1
Parameter Information
6.1.1
Parameter Information Device-Specific Information
6.1.1.1
Signal Transition Levels
6.2
Recommended Clock and Control Signal Transition Behavior
6.3
Power Supplies
6.3.1
Power-On Sequence
6.3.2
Power-Off Sequence
6.4
Reset
6.4.1
Power-On Reset (POR)
6.4.2
Warm Reset
6.4.3
Reset Electrical Data Timings
6.5
Crystal Oscillator or External Clock Input
6.6
Clock PLLs
6.6.1
PLL Device-Specific Information
6.6.2
Device Clock Generation
6.6.3
Dynamic Voltage and Frequency Scaling (DVFS)
6.7
Interrupts
6.7.1
ARM CPU Interrupts
6.7.1.1
ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
6.7.1.2
AINTC Hardware Vector Generation
6.7.1.3
AINTC Hardware Interrupt Nesting Support
6.7.1.4
AINTC System Interrupt Assignments
6.7.1.5
AINTC Memory Map
6.7.2
DSP Interrupts
6.8
Power and Sleep Controller (PSC)
6.8.1
Power Domain and Module Topology
6.8.1.1
Power Domain States
6.8.1.2
Module States
6.9
Enhanced Direct Memory Access Controller (EDMA3)
6.9.1
EDMA3 Channel Synchronization Events
6.9.2
EDMA3 Peripheral Register Descriptions
6.10
External Memory Interface A (EMIFA)
6.10.1
EMIFA Asynchronous Memory Support
6.10.2
EMIFA Synchronous DRAM Memory Support
6.10.3
EMIFA SDRAM Loading Limitations
6.10.4
EMIFA Connection Examples
6.10.5
External Memory Interface Register Descriptions
6.10.6
EMIFA Electrical Data/Timing
Table 6-21
Timing Requirements for EMIFA SDRAM Interface
Table 6-22
Switching Characteristics for EMIFA SDRAM Interface
Table 6-23
Timing Requirements for EMIFA Asynchronous Memory Interface
6.11
DDR2/mDDR Memory Controller
6.11.1
DDR2/mDDR Memory Controller Electrical Data/Timing
6.11.2
DDR2/mDDR Memory Controller Register Description(s)
6.11.3
DDR2/mDDR Interface
6.11.3.1
DDR2/mDDR Interface Schematic
6.11.3.2
Compatible JEDEC DDR2/mDDR Devices
6.11.3.3
PCB Stackup
6.11.3.4
Placement
6.11.3.5
DDR2/mDDR Keep Out Region
6.11.3.6
Bulk Bypass Capacitors
6.11.3.7
High-Speed Bypass Capacitors
6.11.3.8
Net Classes
6.11.3.9
DDR2/mDDR Signal Termination
6.11.3.10
VREF Routing
6.11.3.11
DDR2/mDDR CK and ADDR_CTRL Routing
6.11.3.12
DDR2/mDDR Boundary Scan Limitations
6.12
Memory Protection Units
6.13
MMC / SD / SDIO (MMCSD0, MMCSD1)
6.13.1
MMCSD Peripheral Description
6.13.2
MMCSD Peripheral Register Description(s)
6.13.3
MMC/SD Electrical Data/Timing
Table 6-42
Timing Requirements for MMC/SD (see and )
Table 6-43
Switching Characteristics for MMC/SD (see through )
6.14
Serial ATA Controller (SATA)
6.14.1
SATA Register Descriptions
6.14.2
1. SATA Interface
6.14.2.1
SATA Interface Schematic
6.14.2.2
Compatible SATA Components and Modes
6.14.2.3
PCB Stackup Specifications
6.14.2.4
Routing Specifications
6.14.2.5
Coupling Capacitors
6.14.2.6
SATA Interface Clock Source requirements
6.14.3
SATA Unused Signal Configuration
6.15
Multichannel Audio Serial Port (McASP)
6.15.1
McASP Peripheral Registers Description(s)
6.15.2
McASP Electrical Data/Timing
6.15.2.1
Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-54
Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)
Table 6-55
Timing Requirements for McASP0 (1.0V)
Table 6-56
Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)
Table 6-57
Switching Characteristics for McASP0 (1.0V)
6.16
Multichannel Buffered Serial Port (McBSP)
6.16.1
McBSP Peripheral Register Description(s)
6.16.2
McBSP Electrical Data/Timing
6.16.2.1
Multichannel Buffered Serial Port (McBSP) Timing
Table 6-59
Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V] (see )
Table 6-60
Timing Requirements for McBSP0 [1.0V] (see )
Table 6-61
Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V] (see )
Table 6-62
Switching Characteristics for McBSP0 [1.0V] (see )
Table 6-63
Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V] (see )
Table 6-64
Timing Requirements for McBSP1 [1.0V] (see )
Table 6-65
Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V] (see )
Table 6-66
Switching Characteristics for McBSP1 [1.0V] (see )
Table 6-67
Timing Requirements for McBSP0 FSR When GSYNC = 1 (see )
Table 6-68
Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
6.17
Serial Peripheral Interface Ports (SPI0, SPI1)
6.17.1
SPI Peripheral Registers Description(s)
6.17.2
SPI Electrical Data/Timing
6.17.2.1
Serial Peripheral Interface (SPI) Timing
Table 6-70
General Timing Requirements for SPI0 Master Modes
Table 6-71
General Timing Requirements for SPI0 Slave Modes
Table 6-78
General Timing Requirements for SPI1 Master Modes
Table 6-79
General Timing Requirements for SPI1 Slave Modes
Table 6-80
Additional SPI1 Master Timings, 4-Pin Enable Option
Table 6-81
Additional SPI1 Master Timings, 4-Pin Chip Select Option
6.18
Inter-Integrated Circuit Serial Ports (I2C)
6.18.1
I2C Device-Specific Information
6.18.2
I2C Peripheral Registers Description(s)
6.18.3
I2C Electrical Data/Timing
6.18.3.1
Inter-Integrated Circuit (I2C) Timing
Table 6-87
Timing Requirements for I2C Input
Table 6-88
Switching Characteristics for I2C
6.19
Universal Asynchronous Receiver/Transmitter (UART)
6.19.1
UART Peripheral Registers Description(s)
6.19.2
UART Electrical Data/Timing
Table 6-90
Timing Requirements for UART Receive (see )
Table 6-91
Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
6.20
Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
6.20.1
USB0 [USB2.0] Electrical Data/Timing
Table 6-93
Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see )
6.21
Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
Table 6-95
Switching Characteristics Over Recommended Operating Conditions for USB1 [USB1.1]
6.22
Ethernet Media Access Controller (EMAC)
6.22.1
EMAC Peripheral Register Description(s)
6.22.1.1
EMAC Electrical Data/Timing
Table 6-100
Timing Requirements for MII_RXCLK (see )
Table 6-101
Timing Requirements for MII_TXCLK (see )
Table 6-102
Timing Requirements for EMAC MII Receive 10/100 Mbit/s (see )
Table 6-103
Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (see )
6.23
Management Data Input/Output (MDIO)
6.23.1
MDIO Register Description(s)
6.23.2
Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-107
Timing Requirements for MDIO Input (see and )
Table 6-108
Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
6.24
LCD Controller (LCDC)
6.24.1
LCD Interface Display Driver (LIDD Mode)
6.24.2
LCD Raster Mode
Table 6-112
Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode
6.25
Host-Port Interface (UHPI)
6.25.1
HPI Device-Specific Information
6.25.2
HPI Peripheral Register Description(s)
6.25.3
HPI Electrical Data/Timing
Table 6-114
Timing Requirements for Host-Port Interface [1.2V, 1.1V]
Table 6-115
Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.3V, 1.2V, 1.1V]
Table 6-116
Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]
6.26
Universal Parallel Port (uPP)
6.26.1
uPP Register Descriptions
Table 6-117
Universal Parallel Port (uPP) Registers
6.26.2
uPP Electrical Data/Timing
Table 6-118
Timing Requirements for uPP (see , , , )
Table 6-119
Switching Characteristics Over Recommended Operating Conditions for uPP
6.27
Video Port Interface (VPIF)
6.27.1
VPIF Register Descriptions
Table 6-120
Video Port Interface (VPIF) Registers
6.27.2
VPIF Electrical Data/Timing
Table 6-121
Timing Requirements for VPIF VP_CLKINx Inputs (see )
Table 6-122
Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs (see )
Table 6-123
Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3 (see )
6.28
Enhanced Capture (eCAP) Peripheral
Table 6-125
Timing Requirements for Enhanced Capture (eCAP)
Table 6-126
Switching Characteristics Over Recommended Operating Conditions for eCAP
6.29
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
6.29.1
Enhanced Pulse Width Modulator (eHRPWM) Timing
Table 6-128
Timing Requirements for eHRPWM
Table 6-129
Switching Characteristics Over Recommended Operating Conditions for eHRPWM
6.29.2
Trip-Zone Input Timing
6.30
Timers
6.30.1
Timer Electrical Data/Timing
Table 6-132
Timing Requirements for Timer Input (see )
Table 6-133
Switching Characteristics Over Recommended Operating Conditions for Timer Output
6.31
Real Time Clock (RTC)
6.31.1
Clock Source
6.31.2
Real-Time Clock Register Descriptions
6.32
General-Purpose Input/Output (GPIO)
6.32.1
GPIO Register Description(s)
6.32.2
GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-136
Timing Requirements for GPIO Inputs (see )
Table 6-137
Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
6.32.3
GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-138
Timing Requirements for External Interrupts (see )
6.33
Programmable Real-Time Unit Subsystem (PRUSS)
6.33.1
PRUSS Register Descriptions
6.34
Emulation Logic
6.34.1
JTAG Port Description
6.34.2
Scan Chain Configuration Parameters
6.34.3
Initial Scan Chain Configuration
6.34.3.1
Adding TAPS to the Scan Chain
6.34.4
IEEE 1149.1 JTAG
6.34.4.1
JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
6.34.4.2
JTAG Test-Port Electrical Data/Timing
Table 6-150
Timing Requirements for JTAG Test Port (see )
Table 6-151
Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
6.34.5
JTAG 1149.1 Boundary Scan Considerations
7
Device and Documentation Support
7.1
Device Nomenclature
7.2
Tools and Software
7.3
Documentation Support
7.4
Community Resources
7.5
商標
7.6
静電気放電に関する注意事項
7.7
Export Control Notice
7.8
Glossary
8
Mechanical Packaging and Orderable Information
8.1
Thermal Data for ZCE Package
8.2
Thermal Data for ZWT Package
8.3
Packaging Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ（パッケージ｜ピン）
ZCE|361
ZWT|361
サーマルパッド・メカニカル・データ
発注情報
jajsdv4j_oa
jajsdv4j_pm
6.1
Parameter Information