8.3.1 High-Speed Data Path

The high-speed data signal is applied to the data path by means of input signal pins DIN+ / DIN–. The data path consists of a 100-Ω differential termination resistor followed by a digitally controlled bandwidth switch input buffer for rate select. The RATE1 and RATE0 pins can be used to control the bandwidth of the filter. Default bandwidth settings are used; however, these can be changed using registers 4 through 7 through the serial interface. For details regarding the rate selection, see Table 19. A gain stage and an output buffer stage follow the input buffer, which together provide a gain of 34 dB. The device can accept input amplitude levels from 5 mV_pp up to 2000 mV_pp. The amplified data output signal is available at the output pins DOUT+ and DOUT, which includes on-chip 2 × 50-Ω back-termination to VCC.

Offset cancellation compensates for internal offset voltages and thus ensures proper operation even for very small input data signals. The offset cancellation can be disabled so that the input threshold voltage can be adjusted to optimize the bit error rate or change the eye crossing to compensate for input signal pulse width distortion. The offset cancellation can be disabled by setting OCDIS = 1 (bit 1 of register 0). The input threshold level can be adjusted using register settings THADJ[0..7] (register 1). For details regarding input threshold adjust, see Table 19.

The low frequency cutoff is as low as 80 kHz with the built-in filter capacitor. For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be connected to the COC1 and COC2 pins. A value of 330 pF results in a low frequency cutoff of 10 kHz.

8.3.2 Band-gap Voltage and Bias Generation

The ONET8501PB limiting amplifier is supplied by a single 3.3-V supply voltage connected to the VCC pins. This voltage is referred to ground (GND).

On-chip band-gap voltage circuitry generates a reference voltage, independent of supply voltage, from which all other internally required voltages and bias currents are derived.

8.4.1 High-Speed Output Buffer

The output amplitude of the buffer can be set to 350 mV_pp, 650 mV_pp, or 850 mV_pp using register settings AMP[0..1] (register 3) through the serial interface. To compensate for frequency dependant losses of transmission lines connected to the output, the ONET8501PB has adjustable preemphasis of the output stage. The preemphasis can be set from 0 to 8 dB in 1-dB steps using register settings PEADJ[0..3] (register 2).

8.4.2 Rate Select

There are 16 possible internal filter settings (4 bit) to adjust the small signal bandwidth to the data rate. For fast rate selection, 4 default values can be selected with the RATE1 and RATE0 pins. Using the serial interface, the bandwidth settings can be customized instead of using the default values. The default bandwidths and the registers used to change the bandwidth settings are shown in Table 1.

If the rate select register selection bit is set LOW, for example RSASEL = 0 (bit 7 of register 4), then the default bandwidth for that register is used. If the register selection bit is set HIGH, for example RSASEL = 1 (bit 7 of register 4), then the content of RSA[0..3] (register 4) is used to set the input filter bandwidth when RATE0 = 0 and RATE1 = 0. The settings of the rate selection registers RSA, RSB, RSC, RSD, and the corresponding filter bandwidths are shown in Table 2.

The RATE1 and RATE0 pins do not have to be used if the serial interface is being used. If RATE1 is not connected it is internally pulled HIGH and if RATE0 is not connected it is internally pulled LOW, thus selecting register 7. Therefore, changing the contents of RSD[0..3] (register 7) through the serial interface can be used to adjust the bandwidth.

8.4.3 Loss-of-Signal Detection

The loss of signal detection is done by 2 separate level detectors to cover a wide dynamic range. The peak values of the input signal and the output signal of the gain stage are monitored by the peak detectors. The peak values are compared to a predefined loss of signal threshold voltage inside the loss of signal detection block. As a result of the comparison, the LOS signal, which indicates that the input signal amplitude is below the defined threshold level, is generated. The LOS assert level is settable through the serial interface. There are 2 LOS ranges settable with the LOSRNG bit (bit 2 register 0) through the serial interface. By setting the bit LOSRNG = 1, the high range of the LOS assert values are used (35 mV_pp to 80 mV_pp) and by setting the bit LOSRNG = 0, the low range of the LOS assert values are used (15 mV_pp to 35 mV_pp).

There are 128 possible internal LOS settings (7 bit) for each LOS range to adjust the LOS assert level. For fast LOS selection, 4 default values can be selected with the RATE1 and RATE0 pins; however, the LOS settings can be customized instead of using the default values. The default LOS assert levels and the registers used to change the LOS settings are shown in Table 3.

If the LOS register selection bit is set low, for example LOSASEL = 0 (bit 7 of register 8), then the default LOS assert level for that register is used. If the register selection bit is set high, for example LOSASEL = 1 (bit 7 of register 8), then the content of LOSA[0..6] (register 8) is used to set the LOS assert level when RATE1 = 0 and RATE0 = 0. The RATE1 and RATE0 pins do not have to be used if the serial interface is being used. If RATE1 is not connected it is internally pulled HIGH and if RATE0 is not connected it is internally pulled LOW, thus selecting register 11. Therefore, changing the content of LOSD[0..6] (register 11) through the serial interface can be used to adjust the LOS assert level.

8.5.1 2-Wire Interface and Control Logic

The ONET8501PB uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial clock from a microcontroller, for example. Both inputs include 100-kΩ pullup resistors to VCC. For driving these inputs, TI recommends an open-drain output.

The 2-wire interface allows write access to the internal memory map to modify control registers and read access to read out control and status signals. The ONET8501PB is a slave device only which means that it can not initiate a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The master device provides the clock signal as well as the START and STOP commands. The protocol for a data transmission is as follows:

1. START command
2. 7-bit slave address (1000100) followed by an eighth bit which is the data direction bit (R/W). A zero indicates a WRITE and a 1 indicates a READ.
3. 8-bit register address
4. 8-bit register data word
5. STOP command

Regarding timing, the ONET8501PB is I²C compatible. The typical timing is shown in Figure 13 and a complete data transfer is shown in Figure 14. Parameters for Figure 13 are defined in Table 4.

Bus Idle: Both SDA and SCK lines remain HIGH

Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH, defines a START condition (S). Each data transfer begins with a START condition.

Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH defines a STOP condition (P). Each data transfer ends with a STOP condition; however, if the master still wishes to communicate on the bus, it can generate a repeated START condition and address another slave without first generating a STOP condition.

Data Transfer: Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition.

Figure 13. I²C Timing Diagram

Figure 14. I²C Data Transfer

8.6.1 Register 0 (0x00) Mapping – Control Settings

8.6.2 Register 1 (0x01) Mapping – Input Threshold Adjust

8.6.3 Register 2 (0x02) Mapping – Preemphasis Adjust

8.6.4 Register 3 (0x03) Mapping – Output Amplitude Adjust

8.6.5 Register 4 (0x04) Mapping – Rate Selection Register A

8.6.6 Register 5 (0x05) Mapping – Rate Selection Register B

8.6.7 Register 6 (0x06) Mapping – Rate Selection Register C

8.6.8 Register 7 (0x07) Mapping – Rate Selection Register D

8.6.9 Register 8 (0x08) Mapping – LOS Assert Level Register A

8.6.10 Register 9 (0x09) Mapping – LOS Assert Level Register B

8.6.11 Register 10 (0x0A) Mapping – LOS Assert Level Register C

8.6.12 Register 11 (0x0B) Mapping – LOS Assert Level Register D

8.6.13 Register 14 (0x0E) Mapping – Selected Rate Setting (Read Only)

8.6.14 Register 15 (0x0F) Mapping – Selected LOS Level (Read Only)

Table 19. Register Functionality