SLLS910A July   2008  – June 2016 ONET8501PB

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 DC Electrical Characteristics
    5. 7.5 AC Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High-Speed Data Path
      2. 8.3.2 Band-gap Voltage and Bias Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 High-Speed Output Buffer
      2. 8.4.2 Rate Select
      3. 8.4.3 Loss-of-Signal Detection
    5. 8.5 Programming
      1. 8.5.1 2-Wire Interface and Control Logic
    6. 8.6 Register Maps
      1. 8.6.1  Register 0 (0x00) Mapping - Control Settings
      2. 8.6.2  Register 1 (0x01) Mapping - Input Threshold Adjust
      3. 8.6.3  Register 2 (0x02) Mapping - Preemphasis Adjust
      4. 8.6.4  Register 3 (0x03) Mapping - Output Amplitude Adjust
      5. 8.6.5  Register 4 (0x04) Mapping - Rate Selection Register A
      6. 8.6.6  Register 5 (0x05) Mapping - Rate Selection Register B
      7. 8.6.7  Register 6 (0x06) Mapping - Rate Selection Register C
      8. 8.6.8  Register 7 (0x07) Mapping - Rate Selection Register D
      9. 8.6.9  Register 8 (0x08) Mapping - LOS Assert Level Register A
      10. 8.6.10 Register 9 (0x09) Mapping - LOS Assert Level Register B
      11. 8.6.11 Register 10 (0x0A) Mapping - LOS Assert Level Register C
      12. 8.6.12 Register 11 (0x0B) Mapping - LOS Assert Level Register D
      13. 8.6.13 Register 14 (0x0E) Mapping - Selected Rate Setting (Read Only)
      14. 8.6.14 Register 15 (0x0F) Mapping - Selected LOS Level (Read Only)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resource
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGT Package
16-Pin VQFN
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
COC1 5 Analog Offset cancellation filter capacitor plus terminal. An external capacitor can be connected between this pin and COC2 to reduce the low frequency cutoff. To disable the offset cancellation loop, connect COC1 and COC2 together.
COC2 6 Analog Offset cancellation filter capacitor minus terminal. An external capacitor can be connected between this pin and COC1 to reduce the low frequency cutoff. To disable the offset cancellation loop, connect COC1 and COC2 together.
DIN+ 2 Analog-input Noninverted data input. Differentially 100 Ω terminated to DIN–.
DIN– 3 Analog-input Inverted data input. Differentially 100 Ω terminated to DIN+.
DIS 7 Digital-input Disables the output stage when set to a high level.
DOUT– 10 CML-out Inverted data output. On-chip 50 Ω back-terminated to VCC.
DOUT+ 11 CML-out Noninverted data output. On-chip 50 Ω back-terminated to VCC.
GND 1,4, EP Supply Circuit ground. Exposed die pad (EP) must be grounded.
LOS 8 Open-drain MOS High level indicates that the input signal amplitude is below the programmed threshold level. Open-drain output. Requires an external 10-kΩ pullup resistor to VCC for proper operation.
RATE1 13 Digital-input Bandwidth selection for noise suppression.
RATE0 14 Digital-input Bandwidth selection for noise suppression.
SCK 15 Digital-input Serial interface clock input. Connect a pullup resistor (10 kΩ typical) to VCC.
SDA 16 Digital-input Serial interface data input. Connect a pullup resistor (10 kΩ typical) to VCC.
VCC 9, 12 Supply 3.3-V ± 10% supply voltage.