JAJSGT8F June   2010  – March 2023 OPA140 , OPA2140 , OPA4140

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA140
    5. 6.5 Thermal Information: OPA2140
    6. 6.6 Thermal Information: OPA4140
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operating Voltage
      2. 7.3.2  Capacitive Load and Stability
      3. 7.3.3  Output Current Limit
      4. 7.3.4  Noise Performance
      5. 7.3.5  Basic Noise Calculations
      6. 7.3.6  Phase-Reversal Protection
      7. 7.3.7  Thermal Protection
      8. 7.3.8  Electrical Overstress
      9. 7.3.9  EMI Rejection
      10. 7.3.10 EMIRR +IN Test Configuration
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
        3. 9.1.1.3 フィルタ設計ツール
        4. 9.1.1.4 TI のリファレンス・デザイン
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-A874D42F-D776-4B33-B7AC-0D6C136E3EE6-low.gif Figure 5-1 OPA140: D Package, 8-Pin SOIC and DGK Package, 8-Pin VSSOP (Top View)
GUID-FA9CAC74-936F-430A-AD8F-CD791C1617A0-low.gif Figure 5-2 OPA140: DBV Package, 5-Pin SOT-23 (Top View)
Table 5-1 Pin Functions: OPA140
PIN TYPE DESCRIPTION
NAME OPA140
D (SOIC),
DGK (VSSOP)		 DBV (SOT)
+IN 3 3 Input Noninverting input
–IN 2 4 Input Inverting input
NC 1, 5, 8 — — No internal connection (can be left floating)
OUT 6 1 Output Output
V+ 7 5 — Positive (highest) power supply
V– 4 2 — Negative (lowest) power supply
GUID-E69A3EA4-2BAD-47E3-A9E6-055F58C39DC1-low.gifFigure 5-3 OPA2140: D Package, 8-Pin SOIC and DGK Package, 8-Pin VSSOP (Top View)
GUID-6FC4B43B-F83E-40B4-9CEB-F228F5B86E2B-low.gifFigure 5-5 OPA4140: D Package, 14-Pin SOIC and PW Package, 14-Pin TSSOP (Top View)
GUID-876ADB73-0135-4602-8350-D1A4BE109F1D-low.gifFigure 5-4 OPA2140: DRG Package, 8-Pin SON (Top View)
Table 5-2 Pin Functions: OPA2140 and OPA4140
PIN TYPE DESCRIPTION
NAME OPA2140 OPA4140
D (SOIC),
DGK (VSSOP),
DRG (SON) 		D (SOIC),
PW (TSSOP)
+IN A 3 3 Input Noninverting input, channel A
+IN B 5 5 Input Noninverting input, channel B
+IN C — 10 Input Noninverting input, channel C
+IN D — 12 Input Noninverting input, channel D
–IN A 2 2 Input Inverting input, channel A
–IN B 6 6 Input Inverting input, channel B
–IN C — 9 Input Inverting input, channel C
–IN D — 13 Input Inverting input, channel D
OUT A 1 1 Output Output, channel A
OUT B 7 7 Output Output, channel B
OUT C — 8 Output Output, channel C
OUT D — 14 Output Output, channel D
V+ 8 4 — Positive (highest) power supply
V– 4 11 — Negative (lowest) power supply
Thermal Pad DRG Package only — — Thermal pad is internally connected to V−. Solder the thermal pad to a heat spreading plane on the board connected to V−. For DRG package only.