JAJSGT8F June   2010  – March 2023 OPA140 , OPA2140 , OPA4140

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA140
    5. 6.5 Thermal Information: OPA2140
    6. 6.6 Thermal Information: OPA4140
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operating Voltage
      2. 7.3.2  Capacitive Load and Stability
      3. 7.3.3  Output Current Limit
      4. 7.3.4  Noise Performance
      5. 7.3.5  Basic Noise Calculations
      6. 7.3.6  Phase-Reversal Protection
      7. 7.3.7  Thermal Protection
      8. 7.3.8  Electrical Overstress
      9. 7.3.9  EMI Rejection
      10. 7.3.10 EMIRR +IN Test Configuration
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
        3. 9.1.1.3 フィルタ設計ツール
        4. 9.1.1.4 TI のリファレンス・デザイン
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics

at TA = 25°C, VS = 4.5 V (±2.25) to 36 V (±18 V), RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage  ±30 ±120 μV
VS = ±18 V, TA = –40°C to +125°C ±220
VS = ±2.25 V to ±18 V, TA = –40°C to +125°C ±4 μV/V
dVOS/dT Input offset voltage drift VS = ±18 V, TA = –40°C to +125°C ±0.35 ±1 μV/°C
PSRR Power-supply rejection ratio VS = ±2.25 V to ±18 V, TA = –40°C to +125°C ±0.1 ±0.5 μV/V
INPUT BIAS CURRENT
IB Input bias current ±0.5 ±10 pA
TA = –40°C to +125°C ±3 nA
IOS Input offset current ±0.5 ±10 pA
TA = –40°C to +125°C ±1 nA
NOISE
En Input voltage noise  f = 0.1 Hz to 10 Hz 250 nVPP
f = 0.1 Hz to 10 Hz 42 nVRMS
en Input voltage noise density f = 10 Hz 8 nV/√Hz
f = 100 Hz 5.8
f = 1 kHz 5.1
In Input current noise density f = 1 kHz 0.8 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage TA = –40°C to +125°C (V–) – 0.1 (V+) – 3.5 V
CMRR Common-mode rejection ratio VS = ±18 V, VCM = (V–) – 0.1 V to (V+) – 3.5 V 126 140 dB

TA = –40°C to +125°C		 120
INPUT IMPEDANCE
ZID Differential 1013 || 10 Ω || pF
ZIC Common-mode VCM = (V–) –0.1 V to (V+) –3.5 V 1013 || 7 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VO = (V–) + 0.35 V to (V+) – 0.35 V, RL = 10 kΩ 120 126 dB
VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 2 kΩ		 114 126
TA = –40°C to +125°C 108
FREQUENCY RESPONSE
BW Gain bandwidth product 11 MHz
SR Slew rate 20 V/μs
ts Settling time 12 bits  0.88 μs
16 bits 1.6
tOR Overload recovery time 600 ns
THD+N Total harmonic distortion + noise 1 kHz, G = +1, VO = 3.5 VRMS 0.00005%
OUTPUT
VO Voltage output RL = 10 kΩ, AOL ≥ 108 dB (V–) + 0.2 (V+) – 0.2 V
RL = 2 kΩ, AOL ≥ 108 dB (V–) + 0.35 (V+) – 0.35
ISC Short-circuit current Source 36 mA
Sink –30
CLOAD Capacitive load drive See Typical Characteristics
ZO Open-loop output impedance f = 1 MHz, IO = 0 A (See Typical Characteristics) 16 Ω
POWER SUPPLY
IQ Quiescent current per amplifier  IO = 0 mA 1.8 2 mA
TA = –40°C to +125°C 2.7
CHANNEL SEPARATION
Channel separation At dc 0.02 µV/V
At 100 kHz 10