SBOS484D December   2009  – April 2016 OPA1641 , OPA1642 , OPA1644

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Phase Reversal Protection
      2. 7.3.2 Output Current Limit
      3. 7.3.3 EMI Rejection Ratio (EMIRR)
        1. 7.3.3.1 EMIRR IN+ Test Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Voltage
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noise Performance
      2. 8.1.2 Basic Noise Calculations
      3. 8.1.3 Total Harmonic Distortion Measurements
      4. 8.1.4 Source Impedance and Distortion
      5. 8.1.5 Capacitive Load and Stability
      6. 8.1.6 Power Dissipation and Thermal Protection
      7. 8.1.7 Electrical Overstress
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH® Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS Supply voltage 40 V
VIN Input voltage(2) (V–) – 0.5 (V+) + 0.5 V
IIN Input current(2) ±10 mA
VIN(DIFF) Differential input voltage ±VS V
IO Output short-circuit(3) Continuous
TA Operating temperature –55 125 °C
TJ Junction temperature –65 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current-limited to 10 mA or less. The input voltage and output negative-voltage ratings can be exceeded if the input and output current ratings are followed.
(3) Short-circuit to VS / 2 (ground in symmetrical dual-supply setups), one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage (V+, V–) Single supply 4.5 36 V
Dual supply ±2.25 ±18
Specified temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) OPA1641, OPA1642 OPA1644 UNIT
D (SOIC) DGK (VSSOP) D (SOIC) PW (TSSOP)
8 PINS 8 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 160 180 97 135 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 75 55 56 45 °C/W
RθJB Junction-to-board thermal resistance 60 130 53 66 °C/W
ψJT Junction-to-top characterization parameter 9 n/a 19 n/a °C/W
ψJB Junction-to-board characterization parameter 50 120 46 60 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

at TA = 25°C, VS = 4.5 V to 36 (±2.25 V to ±18 V), RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO PERFORMANCE
THD+N Total harmonic distortion + noise G = +1, f = 1 kHz, VO = 3 VRMS 0.00005%
–126 dB
IMD Intermodulation distortion SMPTE/DIN two-tone, 4:1
(60 Hz and 7 kHz), G = +1,
VO = 3 VRMS		 0.00004%
–128 dB
DIM 30 (3-kHz square wave and
15-kHz sine wave), G = +1,
VO = 3 VRMS		 0.00008%
–122 dB
CCIF twin-tone
(19 kHz and 20 kHz), G = +1,
VO = 3 VRMS		 0.00007%
–123 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product G = 1 11 MHz
SR Slew rate G = 1 20 V/μs
Full-power bandwidth(1) VO = 1 VP 3.2 MHz
Overload recovery time(2) G = –10 600 ns
Channel separation (dual and quad) f = 1 kHz –126 dB
NOISE
Input voltage noise f = 20 Hz to 20 kHz 4.3 μVPP
en Input voltage noise density f = 10 Hz 8 nV/√Hz
f = 100 Hz 5.8
f = 1 kHz 5.1
In Input current noise density f = 1 kHz 0.8 fA/√Hz
OFFSET VOLTAGE
VOS Input offset voltage VS = ±18 V 1 3.5 mV
PSRR VOS vs power supply VS = ±2.25 V to ±18 V 0.14 2 μV/V
INPUT BIAS CURRENT
IB Input bias current VCM = 0 V ±2 ±20 pA
IOS Input offset current VCM = 0 V ±2 ±20 pA
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–)–0.1 (V+)–3.5 V
CMRR Common-mode rejection ratio VCM = (V–) – 0.1 V to (V+) – 3.5 V,
VS = ±18 V		 120 126 dB
INPUT IMPEDANCE
Differential 1013 || 8 Ω || pF
Common-mode VCM = (V–) – 0.1 V to (V+) – 3.5 V 1013 || 6 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.2 V ≤ VO ≤ (V+) – 0.2 V,
RL = 10 kΩ		 120 134 dB
(V–) + 0.35 V ≤ VO ≤ (V+) – 0.35 V,
RL = 2 kΩ		 114 126
OUTPUT
VO Voltage output swing from rail RL = 10 kΩ, AOL ≥ 120 dB (V–)+0.2 (V+)–0.2 V
RL = 2 kΩ, AOL ≥ 114 dB (V–)+0.35 (V+)–0.35
IOUT Output current See Typical Characteristics
ZO Open-loop output impedance See Typical Characteristics
ISC Short-circuit current Source 36 mA
Sink –30
CLOAD Capacitive load drive See Typical Characteristics
POWER SUPPLY
VS Specified voltage ±2.25 ±18 V
IQ Quiescent current (per amplifier) IOUT = 0 A 1.8 2.3 mA
TEMPERATURE RANGE
Specified range –40 85 °C
Operating range –55 125 °C
Thermal resistance 8-pin SOIC package 138 °C/W
8-pin VSSOP package 180
14-pin SOIC package 97
14-pin TSSOP package 135
(1) Full power bandwidth = SR / (2π × VP), where SR = slew rate.
(2) See Figure 19 and Figure 20.

6.6 Typical Characteristics

at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
OPA1641 OPA1642 OPA1644 tc_v_noise_dens_fqcy_bos484.gif
Figure 1. Input Voltage Noise Density vs Frequency
OPA1641 OPA1642 OPA1644 tc_vout_max_freq_bos484.gif
Figure 3. Maximum Output Voltage vs Frequency
OPA1641 OPA1642 OPA1644 tc_gain_phase_fqcy_bos484.gif
Figure 5. Gain and Phase vs Frequency
OPA1641 OPA1642 OPA1644 tc_thdn_fqcy_01_bos484.gif
Figure 7. THD+N Ratio vs Frequency
OPA1641 OPA1642 OPA1644 tc_thdn_vout_amp_bos484.gif
Figure 9. THD+N Ratio vs Output Amplitude
OPA1641 OPA1642 OPA1644 tc_chan_sep_fqcy_bos484.gif
Figure 11. Channel Separation vs Frequency
OPA1641 OPA1642 OPA1644 tc_sm_signal_step_g1_bos484.gif
Figure 13. Small-Signal Step Response (100 mV)
OPA1641 OPA1642 OPA1644 tc_lg_signal_step_g1_bos484.gif
Figure 15. Large-Signal Step Response
OPA1641 OPA1642 OPA1644 tc_pos_overload_recovery_bos484.gif
Figure 17. Positive Overload Recovery
OPA1641 OPA1642 OPA1644 tc_sm_sig_ovrsht_cload_01_bos484.gif
Figure 19. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
OPA1641 OPA1642 OPA1644 tc_aol_temp_bos484.gif
Figure 21. Open-Loop Gain vs Temperature
OPA1641 OPA1642 OPA1644 tc_ib_ios_cm_v_bos484.gif
Figure 23. IB and IOS vs Common-Mode Voltage
OPA1641 OPA1642 OPA1644 tc_iq_vsupply_bos484.gif
Figure 25. Quiescent Current vs Supply Voltage
OPA1641 OPA1642 OPA1644 tc_vout_iout_bos484.gif
Figure 27. Output Voltage vs Output Current
OPA1641 OPA1642 OPA1644 tc_noise_bos484.gif
Figure 2. 0.1-Hz to 10-Hz Noise
OPA1641 OPA1642 OPA1644 tc_cmrr_psrr_fqcy_bos484.gif
Figure 4. CMRR and PSRR vs Frequency
(Referred to Input)
OPA1641 OPA1642 OPA1644 tc_closed_lp_gain_fqcy_bos484.gif
Figure 6. Closed-Loop Gain vs Frequency
OPA1641 OPA1642 OPA1644 tc_thdn_fqcy_03_bos484.gif
Figure 8. THD+N Ratio vs Frequency
OPA1641 OPA1642 OPA1644 tc_imd_out_amp_bos484.gif
Figure 10. Intermodulation Distortion
vs Output Amplitude
OPA1641 OPA1642 OPA1644 tc_phase_reverse_bos484.gif
Figure 12. No Phase Reversal
OPA1641 OPA1642 OPA1644 tc_sm_signal_step_g-1_bos484.gif
Figure 14. Small-Signal Step Response (100 mV)
OPA1641 OPA1642 OPA1644 tc_lg_signal_step_g-1_bos484.gif
Figure 16. Large-Signal Step Response
OPA1641 OPA1642 OPA1644 tc_neg_overload_recovery_bos484.gif
Figure 18. Negative Overload Recovery
OPA1641 OPA1642 OPA1644 tc_sm_sig_ovrsht_cload_02_bos484.gif
Figure 20. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
OPA1641 OPA1642 OPA1644 tc_ib_ios_temp_bos484.gif
Figure 22. IB and IOS vs Temperature
OPA1641 OPA1642 OPA1644 tc_iq_temp_bos484.gif
Figure 24. Quiescent Current vs Temperature
OPA1641 OPA1642 OPA1644 tc_isc_temp_bos484.gif
Figure 26. Short-Circuit Current vs Temperature
OPA1641 OPA1642 OPA1644 tc_oloop_freq_bos484.gif
Figure 28. Open-Loop Output Impedance vs Frequency