JAJSNV3C june   2022  – july 2023 OPA186 , OPA2186 , OPA4186

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA186
    5. 6.5 Thermal Information: OPA2186
    6. 6.6 Thermal Information: OPA4186
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Rail-to-Rail Inputs
      2. 7.3.2 Phase-Reversal Protection
      3. 7.3.3 Input Bias Current Clock Feedthrough
      4. 7.3.4 EMI Rejection
        1. 7.3.4.1 EMIRR +IN Test Configuration
      5. 7.3.5 Electrical Overstress
      6. 7.3.6 MUX-Friendly Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Noise Calculations
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Current Sensing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bridge Amplifier
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-310FCD32-44E3-4D2C-9BAA-75C379FCF47B-low.gifFigure 5-1 OPA186: D Package, 8-Pin SOIC (Top View)
GUID-3D8C81EA-E028-4B65-A95F-9E3F1D4E3C75-low.gifFigure 5-2 OPA186: DBV Package, 5-Pin SOT-23 (Top View)
Table 5-1 Pin Functions: OPA186
PIN TYPE DESCRIPTION
NAME NO.
D (SOIC) DBV (SOT-23)
–IN 4 2 Input Inverting input
+IN 3 3 Input Noninverting input
OUT 1 6 Output Output
V– 2 4 Power Negative (lowest) power supply
V+ 5 7 Power Positive (highest) power supply
NC — 1, 8, 5 — No connection (can be left floating)
GUID-AD39F322-58A8-4A13-A23E-9FE0DC383B4A-low.gifFigure 5-3 OPA2186: D Package, 8-Pin SOIC and DDF Package, 8-Pin SOT-23 (Top View)
Table 5-2 Pin Functions: OPA2186
PIN TYPE DESCRIPTION
NAME NO.
–IN A 2 Input Inverting input channel A
+IN A 3 Input Noninverting input channel A
–IN B 6 Input Inverting input channel B
+IN B 5 Input Noninverting input channel B
OUT A 1 Output Output channel A
OUT B 7 Output Output channel B
V– 4 Power Negative supply
V+ 8 Power Positive supply
GUID-D98F8CE4-278B-42D8-8995-73AB174C0DF1-low.gifFigure 5-4 OPA4186: D Package, 14-Pin SOIC (Top View)
Table 5-3 Pin Functions: OPA4186
PIN TYPE DESCRIPTION
NAME NO.
–IN A 2 Input Inverting input channel A
+IN A 3 Input Noninverting input channel A
–IN B 6 Input Inverting input channel B
+IN B 5 Input Noninverting input channel B
–IN C 9 Input Inverting input channel C
+IN C 10 Input Noninverting input channel C
–IN D 13 Input Inverting input channel D
+IN D 12 Input Noninverting input channel D
OUT A 1 Output Output channel A
OUT B 7 Output Output channel B
OUT C 8 Output Output channel C
OUT D 14 Output Output channel D
V– 11 Power Negative supply
V+ 4 Power Positive supply