JAJSD62C March   2013  – January 2020 OPA188

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      自動ゼロ化技術による、非常に低い温度ドリフト係数の実現
  4. 4 改訂履歴
  5. 5 Device Comparison Table
    1. 5.1 Portfolio Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: High-Voltage Operation
    6. 7.6 Electrical Characteristics: Low-Voltage Operation
    7. 7.7 Typical Characteristics: Table of Graphs
      1. 7.7.1 Table of Graphs
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Characteristics
      2. 8.3.2 Phase-Reversal Protection
      3. 8.3.3 Input Bias Current Clock Feedthrough
      4. 8.3.4 Internal Offset Correction
      5. 8.3.5 EMI Rejection
      6. 8.3.6 Capacitive Load and Stability
      7. 8.3.7 Electrical Overstress
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 High-Side Voltage-to-Current (V-I) Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Discrete INA + Attenuation for ADC With 3.3-V Supply
      3. 9.2.3 Bridge Amplifier
      4. 9.2.4 Low-Side Current Monitor
      5. 9.2.5 Programmable Power Supply
      6. 9.2.6 RTD Amplifier With Linearization
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 TINA-TI(無償のダウンロード・ソフトウェア)
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.8 Typical Characteristics

at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
OPA188 tc_histo_voff_bos642.gif
Figure 1. Offset Voltage Production Distribution
OPA188 tc_vo-tmp_bos642.gif
Figure 3. Offset Voltage vs Temperature
OPA188 tc_vos-vcm_18v_bos525.gif
Figure 5. Offset Voltage vs Common-Mode Voltage
OPA188 C007_SBOS642.png
Figure 7. Open-Loop Gain and Phase vs Frequency
OPA188 tc_ib_ios-vcm_bos642.gif
Figure 9. IB and IOS vs Common-Mode Voltage
OPA188 tc_vo_swing-io_bos642.gif
Figure 11. Output Voltage Swing vs
Output Current (Maximum Supply)
OPA188 tc_cmrr-tmp_2v_bos642.gif
Figure 13. CMRR vs Temperature
OPA188 tc_psrr-tmp_bos642.gif
Figure 15. PSRR vs Temperature
OPA188 tc_noise_spec-frq_bos525.gif
Figure 17. Input Voltage Noise Spectral Density vs Frequency
OPA188 tc_thdn-outamp_bos642.gif
Figure 19. THD+N vs Output Amplitude
OPA188 tc_iq-tmp_bos642.gif
Figure 21. Quiescent Current vs Temperature
OPA188 tc_oloop_iout-frq_bos642.gif
Figure 23. Open-Loop Output Impedance vs Frequency
OPA188 tc_sm_oshoot-cl_neg_bos642.gif
Figure 25. Small-Signal Overshoot vs
Capacitive Load (100-mV Output Step)
OPA188 tc_oload_pos_bos642.gif
Figure 27. Positive Overload Recovery
OPA188 tc_sm_step_pos_bos525.gif
Figure 29. Small-Signal Step Response
(100 mV)
OPA188 tc_lg_step_pos_bos525.gif
Figure 31. Large-Signal Step Response
OPA188 tc_lg_t_pos_bos642.gif
Figure 33. Large-Signal Settling Time
(10-V Positive Step)
OPA188 tc_isc-tmp_bos642.gif
Figure 35. Short-Circuit Current vs Temperature
OPA188 tc_emirr-frq_bos525.gif
Figure 37. EMIRR IN+ vs Frequency
OPA188 tc_histo_voff_drift_bos642.gif
Figure 2. Offset Voltage Drift Distribution
OPA188 tc_vos-vcm_2v_bos525.gif
Figure 4. Offset Voltage vs Common-Mode Voltage
OPA188 tc_vos-vsupply_bos525.gif
Figure 6. Offset Voltage vs Power Supply
OPA188 tc_cloop_g-frq_bos642.gif
Figure 8. Closed-Loop Gain vs Frequency
OPA188 tc_ibias-tmp_bos642.gif
Figure 10. Input Bias Current vs Temperature
OPA188 tc_cmrr_psrr-frq_bos642.gif
Figure 12. CMRR and PSRR vs Frequency
(Referred-to-Input)
OPA188 tc_cmrr-tmp_18v_bos642.gif
Figure 14. CMRR vs Temperature
OPA188 C016_SBOS642.gif
Figure 16. 0.1-Hz to 10-Hz Noise
OPA188 tc_thdn-frq_bos642.gif
Figure 18. THD+N Ratio vs Frequency
OPA188 tc_iq-vs_bos525.gif
Figure 20. Quiescent Current vs Supply Voltage
OPA188 tc_oloop_g-tmp_bos642.gif
Figure 22. Open-Loop Gain vs Temperature
OPA188 tc_sm_oshoot-cl_pos_bos642.gif
Figure 24. Small-Signal Overshoot vs
Capacitive Load (100-mV Output Step)
OPA188 tc_no_phase_bos525.gif
Figure 26. No Phase Reversal
OPA188 tc_oload_neg_bos642.gif
Figure 28. Negative Overload Recovery
OPA188 tc_sm_step_neg_bos642.gif
Figure 30. Small-Signal Step Response
(100 mV)
OPA188 tc_lg_step_neg_bos525.gif
Figure 32. Large-Signal Step Response
OPA188 tc_lg_t_neg_bos642.gif
Figure 34. Large-Signal Settling Time
(10-V Negative Step)
OPA188 tc_max_vo-frq_bos525.gif
Figure 36. Maximum Output Voltage vs Frequency