JAJSDJ5 July   2017 OPA196 , OPA2196 , OPA4196

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA196
    5. 6.5 Thermal Information: OPA2196
    6. 6.6 Thermal Information: OPA4196
    7. 6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
    8. 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Protection Circuitry
      2. 7.3.2 EMI Rejection
      3. 7.3.3 Phase Reversal Protection
      4. 7.3.4 Thermal Protection
      5. 7.3.5 Capacitive Load and Stability
      6. 7.3.6 Common-Mode Voltage Range
      7. 7.3.7 Electrical Overstress
      8. 7.3.8 Overload Recovery
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Low-side Current Measurement
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 16-Bit Precision Multiplexed Data-Acquisition System
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Slew Rate Limit for Input Protection
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 TINA-TI(無料のダウンロード・ソフトウェア)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DBV Package: OPA196
5-Pin SOT
Top View
OPA196 OPA2196 OPA4196 DAPPER_Single_SOT23.gif
D and DGK Packages: OPA196
8-Pin SOIC and VSSOP
Top View
OPA196 OPA2196 OPA4196 DAPPER_Single_DIP.gif
D and DGK Packages: OPA2196
8-Pin SOIC and VSSOP
Top View
OPA196 OPA2196 OPA4196 DAPPER_Dual_DIP.gif
D and PW Packages: OPA4196
14-Pin SOIC and TSSOP
Top View
OPA196 OPA2196 OPA4196 DAPPER_Quad_DIP.gif
1. NC = No internal connection.

Pin Functions: OPA196

PIN I/O DESCRIPTION
NAME OPA196
D (SOIC),
DGK (VSSOP)		 DBV (SOT)
+IN 3 3 I Noninverting input
–IN 2 4 I Inverting input
NC 1, 5, 8 — — No internal connection (can be left floating)
OUT 6 1 O Output
V+ 7 5 — Positive (highest) power supply
V– 4 2 — Negative (lowest) power supply

Pin Functions: OPA2196 and OPA4196

PIN I/O DESCRIPTION
NAME OPA2196 OPA4196
D (SOIC),
DGK (VSSOP)		 D (SOIC),
PW (TSSOP)
+IN A 3 3 I Noninverting input, channel A
+IN B 5 5 I Noninverting input, channel B
+IN C — 10 I Noninverting input, channel C
+IN D — 12 I Noninverting input, channel D
–IN A 2 2 I Inverting input, channel A
–IN B 6 6 I Inverting input, channel B
–IN C — 9 I Inverting input,,channel C
–IN D — 13 I Inverting input, channel D
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
OUT C — 8 O Output, channel C
OUT D — 14 O Output, channel D
V+ 8 4 — Positive (highest) power supply
V– 4 11 — Negative (lowest) power supply